problem FT2232 sync FIFO mode

[tonyfr]

Hello all,

I have a problem with the nexys vedio board FT2332h chip programming trying to use the FIFO synchronous Mode.

i need to transfer data from PC to FPGA with FT_write(), transfer data from FPGA to PC zith FT_read(). and then continue transfer the next 4K data from PC to FPGA .

In HDL code: if rxen = 0, then oen = 0 , then rdn = 0, strart to receive data on FPGA, if the data size = 4K and txen = 0, start to send data on FPGA, wrn = 0; if the data size = 4K , jump to next receive state.

First problem, the process will lose 2 bytes data every 510 bytes data, that mean i can not receive the 511st the 512 byte data;

Second problem, i can not write the 4K data into the FPGA, the application show that the "write bulk fail" , but i can write less than 510 bytes data into the FPGA and read back currently;

it is current to finish transfer data at one direction, such as just transfer data from PC to FPGA or transfer data from FPGA to PC, no matter how many bytes.

I wonder if someone with some experience of this could give me a few pointers.

Thank you very much for you help.

[D@n]

@tonyfr,

I notice that the Digilent staff have read your e-mail and not commented on it.  Perhaps I might provide some insight while they are consuling with their lawyers

The FTDI interface between the host and the FPGA is a proprietary interface.  For ... various reasons--most of them outside of Digilent's control, Digilent has chosen not to release that interface publicly.  This means that every schematic has a page (or two) missing.  You'll see people requesting that page every now and then on this forum, only to be told the page is missing.  If you look at Xilinx's configuration manual, you should be able to figure out that the FTDI chip must connect to the UART RXD and TXD lines, the JTAG lines, and the DONE and PROG wires of the FPGA.    You'll also know that this chip must connect to the D+ and D- lines of the USB.  That's about all that can be inferred.

The other reality of this is that Digilent does not provide any support beyond the FTDI binary file for the FTDI code running on that FT2232 chip.  For those people who make the mistake of accidentally (or perhaps not so accidentally) reprogramming the chip, Digilent is usually kind enough to provide the instructions and data necessary to reflash the FTDI chip back into a working order.  I get the feeling that reprogramming this chip breaks the warrantee on your board, but the Digilent staff have been kind enough to help folks in that situation.

Sorry I can't be of any further help, but these are the observations I have made from watching this forum over the last year,

Dan

[tonyfr]

@D@n

hello, thank you for replay.

I know the schematic page missing

I just want to transfer data between PC and FPGA, and as describe on the NEXYS VEDIO datasheet, the PC-FPGA Data Transfer (DPTI / DSPI) is micro-usb (J12) and the chip is FT2232h, i just wonder why i can not transfer data as describe signal and timing in the datasheet.

[D@n]

@tonyfr,

Can't you just use the UART port like a regular serial port an communicate with your board?  What are you trying to do different/special where that won't work?

Dan

[tonyfr]

@D@n

hi,

no different work, just large data need to transfer, and UART port is slow.

Maybe i need to check my VHDL code and my timing constrain file.

[D@n]

What baud rate are you running the UART at?  I've had it running at 4MBaud before (400kBps), and always imagined I might take it much higher.

Dan

[tonyfr]

@D@n

Hi,

i am new to FPGA-PC communication.

i need to transfer the image data from PC to FPGA frame by frame, and receive one frame data, then process the data, then send back the result to the PC, then receive the next frame data.

I have tried to use UART port to transfer at 115200 baud from FPGA to PC.

Because i need to check the receiving data and change the state between receive/send data state, need some handshake signal, i think UART is not a good choice.

[D@n]

No, UART is not a good choice for high-speed comms between a CPU and an FPGA.  If you try going through the FTDI chip, it'll be what you are stuck with.

How about firing up that GigE chip on your board and using that?

Dan

[tonyfr]

@D@n

yes, i have struggled in this problem for some days. and i have do my best to solve it, but not work.

about the Gige chip, maybe it is a good way, but i need to finish the application on PC by myself, and i am not good at it, maybe it need some time.

Thank you for you advice, maybe i need to try the Gige chip.

 

tonyfr

[D@n]

Well, if you are going to stick with the UART for a while, let me offer you some of my own work ... since the FTDI chip dumps data onto the UART port, and you aren't necessarily certain if you have the UART communication right (yet), consider the wbuart32 project on GitHub.  One of the really cool things about this project is that it has a Verilator supported simulator attached to it, and reflects the UART port under test either to the terminal or a TCP/IP port of your choice.  I've used this often to test my own designs, especially when the interface is under question.  (Since it runs using Verilator, it works with Verilog only, no HDL or Xilinx specific/proprietary cores ... sorry) 

The other thing I might offer you is that I recall reading (somewhere) that other UART frequencies were available, other than the standard ones, but they required a special IOCTL.  That IOCTL would then remap a standard baud rate to a non-standard number (8MBaud for example?) which could then be used.

In my case, I never transmitted using the full 8-bit value, I was always transmitting readable text across the port.  That allowed me to shave another bit by running the port in 7-bit mode instead of 8-bit mode.  (4MBaud then yields 444kBps, rather than 400kBps, but this may not be enough of a gain to speak of.)

If neither of these ideas work, I suppose you could try compression.  I've used a simple table lookup before for values in the last N.  Sure, it'll cost you a clock per table value of lookup, but it is doable.

Dan

P.S.  I could offer you example code for the RMII interface, but I've just never done the RGMII interface (yet).

[tonyfr]

@D@n

Thank you very much for you help.

i will read the code example on the Github first. And try to use the Gige chip.

Thank you very much.

tonyfr