I'm assessing what's possible when using the pattern generator to provide simulated bus addressing for a uP system, whilst concurrently using the LA to observe and decode that bus plus an 8-bit data bus. I'm using v3.23.4 of Waveforms, in Demo mode (DDiscovery device selected).
What I'm seeing is that Patterns gets to use DIO24 thru 39, whilst the LA DIO0 thru 31. Hence, the 'overlap' is just 8 IO pins, which becomes the maximum single bus width that I can simultaneously stimulate and capture. My DUT requires a minimum of an 11-bit address bus.
Is this just a limitation of the demo mode, or it it an accurate reflection of physical limitations of the Digital Discovery?
Question
bitwise
Hello.
I'm assessing what's possible when using the pattern generator to provide simulated bus addressing for a uP system, whilst concurrently using the LA to observe and decode that bus plus an 8-bit data bus. I'm using v3.23.4 of Waveforms, in Demo mode (DDiscovery device selected).
What I'm seeing is that Patterns gets to use DIO24 thru 39, whilst the LA DIO0 thru 31. Hence, the 'overlap' is just 8 IO pins, which becomes the maximum single bus width that I can simultaneously stimulate and capture. My DUT requires a minimum of an 11-bit address bus.
Is this just a limitation of the demo mode, or it it an accurate reflection of physical limitations of the Digital Discovery?
2 answers to this question
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