amilashanaka Posted November 6 Posted November 6 i found inside ip has pin mapping to PMOD pmod_bridge_0 PmodAD1_pmod_bridge_0_0 (.in0_I(), .in0_O(ad1_cs), .in0_T(1'b0), .in1_I(ad1_sdin0), .in1_O(), .in1_T(1'b1), .in2_I(ad1_sdin1), .in2_O(), .in2_T(1'b1), .in3_I(), .in3_O(ad1_sclk), .in3_T(1'b0), .out0_I(Pmod_out_pin1_i), .out0_O(Pmod_out_pin1_o), .out0_T(Pmod_out_pin1_t), .out1_I(Pmod_out_pin2_i), .out1_O(Pmod_out_pin2_o), .out1_T(Pmod_out_pin2_t), .out2_I(Pmod_out_pin3_i), .out2_O(Pmod_out_pin3_o), .out2_T(Pmod_out_pin3_t), .out3_I(Pmod_out_pin4_i), .out3_O(Pmod_out_pin4_o), .out3_T(Pmod_out_pin4_t), .out4_I(Pmod_out_pin7_i), .out4_O(Pmod_out_pin7_o), .out4_T(Pmod_out_pin7_t), .out5_I(Pmod_out_pin8_i), .out5_O(Pmod_out_pin8_o), .out5_T(Pmod_out_pin8_t), .out6_I(Pmod_out_pin9_i), .out6_O(Pmod_out_pin9_o), .out6_T(Pmod_out_pin9_t), .out7_I(Pmod_out_pin10_i), .out7_O(Pmod_out_pin10_o), .out7_T(Pmod_out_pin10_t) ); without using pin mapping can i use flowing signals with constraints, output wire ad1_cs, input wire ad1_sdin0, input wire ad1_sdin1, output wire ad1_sclk, output wire [1:0] led, set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports {ad1_cs_0 }]; #IO_L17P_T2_34 Sch=ja_p[1] set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports {ad1_sdin0_0}]; #IO_L17N_T2_34 Sch=ja_n[1] set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports {ad1_sdin1_0}]; #IO_L7P_T1_34 Sch=ja_p[2] set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports {ad1_sclk_0}]; #IO_L7N_T1_34 Sch=ja_n[2] where pmod ad1 conect to Ja port in coraz7 board Boneoh 1
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