Analog input ports in Cora-Z7 Master XDC on GitHub need better names

[Viktor Nikolov]

During work on my XADC tutorial, I stumbled upon an imperfection of the Cora-Z7-07S-Master.xdc and Cora-Z7-10-Master.xdc constraints files on the Digilent GitHub regarding the naming of the analog input ports.

This is an excerpt from Cora-Z7-07S-Master.xdc on GitHub:

## Dedicated Analog Inputs
#set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
#set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n

## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]

This is the same excerpt but from the XDC file provided in the Cora Z7 XADC Demo:

## Dedicated Analog Inputs
set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { Vp_Vn_0_v_p }]; #VP_0 Sch=xadc_v_p
set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS33 } [get_ports { Vp_Vn_0_v_n }]; #VN_0 Sch=xadc_v_n

## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_p  }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_n  }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]

As you can see, the XADC demo provides "more complicated" port names and this is for a very good reason.

The easiest way to create an external analog input port in the diagram in Vivado is to right-click on the input analog signal of the XADC Wizard and select Make External. This will create ports like in the attached screenshot.

When you have the ports in the constraint file named Vp_Vn_0_v_p/Vp_Vn_0_v_n and Vaux1_0_v_p/Vaux1_0_v_n, then synthesis and implementation will go without issues.

However, when you have the names of ports v_p/v_n and vaux1_p/vaux1_n as on GitHub, you will get a confusing error during implementation, which will go away only after you rename the ports as the Cora Z7 XADC Demo does it.

Changing analog input port names on GitHub to match the ones in Cora Z7 XADC Demo may be good. 😃

Edited October 27 by Viktor Nikolov
typo fixed

[artvvb]

Hey Viktor,

I don't have a Cora board on hand at the moment that I can test a project with (one is on the way), but I'd be really curious if you see the same behavior. A bitstream builds just fine without any of the input constraints for XADC pins. A bit surprising, but seems logical given that individual numbered channels are connected to fixed locations on the part package, and I believe can be enabled/disabled as desired through the AXI/DRP interface. Minimal screenshot below:

Thanks,

Arthur

[Viktor Nikolov]

Hi @artvvb,

Initially, I also thought you could omit the XADC channels' ports in the constraints.
It works for the dedicated analog input channel VP/VN.
It works that way for auxiliary channels only if you don't use other pins from Bank 35.

I needed the buttons in my design. On Cora Z7, the buttons are connected to the pins from Bank 35.

When I remove the constraint definition for the auxiliary channel, I get an error during implementation. See the attachment.
Adding the constraints removes the error.

set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_p  }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { Vaux1_0_v_n  }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]

It's a bit confusing that defining the IOSTANDARD as LVCMOS33 makes Vivado happy (the XADC channel limitation is 1 V). Nevertheless, it works. 😃

Thanks for raising this topic. I will add a note to the tutorial to explain this to the people.

Viktor

[artvvb]

Ah, makes sense, I hadn't included other pins on the same bank in the test project! So Vivado sees that the pins are used and tries to apply a default bank voltage, which is not overridden by the IO standards set for other pins in the same bank. The IO standard selected needs to be compliant with the bank voltage provided by the power supply, but because we're not using them as digital I/Os, the digital IO standard selected shouldn't affect much physically.

I'll see about getting the Cora template XDC files updated to make the tutorial easier to follow along with - historically, these files are more intended for use with HDL-only projects rather than with block designs, so "readable" (pretty subjective) recommended names are prioritized over easy compatibility with IP. But, there's no board file support for the XADC, and the Cora, as a Zynq board, is more focused on being used with the processor anyway. Worth it here to help simplify an already involved tutorial.

[Viktor Nikolov]

Thank you @artvvb.

I updated the XADC tutorial, so it now uses the Cora Z7 constraints file from the Digilent repository. 👍

Edited November 19 by Viktor Nikolov