I am now trying to figure out how to realize data communication between FPGA and processor in the same Zed board. I have a couple of questions:
1) I know we can use FPGA write OCM on PS through AXI interface. We can easily enable an AXI HP port of PS in block design. But, how can we configure OCM rather than DDR as the destination?
Also what AXI IP core needs to be used in PL? I find some uses AXI register slice, some uses AXI data FIFO.
2) What functions need to be used in the software so that the processor can read data from OCM?
3) Is there any reference design that helps me to complete my design? I have searched online and found that most of the reference design only introduced how to use AXI GPIO or how to use FPGA to write DRAM.
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vvk
Hi,
I am now trying to figure out how to realize data communication between FPGA and processor in the same Zed board. I have a couple of questions:
1) I know we can use FPGA write OCM on PS through AXI interface. We can easily enable an AXI HP port of PS in block design. But, how can we configure OCM rather than DDR as the destination?
Also what AXI IP core needs to be used in PL? I find some uses AXI register slice, some uses AXI data FIFO.
2) What functions need to be used in the software so that the processor can read data from OCM?
3) Is there any reference design that helps me to complete my design? I have searched online and found that most of the reference design only introduced how to use AXI GPIO or how to use FPGA to write DRAM.
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