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communication between FPGA and processor in same board


vvk

Question

Hi,

I am now trying to figure out how to realize data communication between FPGA and processor in the same Zed board. I have a couple of questions:

1) I know we can use FPGA write OCM on PS through AXI interface. We can easily enable an AXI HP port of PS in block design. But, how can we configure OCM rather than DDR as the destination?

    Also what AXI IP core needs to be used in PL? I find some uses AXI register slice, some uses AXI data FIFO. 

2)  What functions need to be used in the software so that the processor can read data from OCM?

3) Is there any reference design that helps me to complete my design? I have searched online and found that most of the reference design only introduced how to use AXI GPIO or how to use FPGA to write DRAM.

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1) You target OCM vs DRAM by using different addresses in your AXI read/write requests. Adam Taylor has a blog entry about the OCM address ranges, which are configurable:

   https://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-49-Using-the-Zynq-SoC-s/ba-p/518579

2) Assuming you are reading/writing OCM from applications, you will need to be able to mmap() OCM into your application processes. Are you running Linux on the Zynq PS?

Here is the Linux driver for OCM: https://github.com/Xilinx/linux-xlnx/blob/master/arch/arm/mach-zynq/zynq_ocm.c

3) Once you get the previous two parts working, it should be just like communicating through DRAM but with lower latency and probably higher bandwidth. But if there are other parts you have questions with, please post the questions here.

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I am attempting to have the two ARM cores in  ZedBoard xc7z020 interact with one another via fpga (PL)core. I want to send the data with a speed of 1Gbps from  first ARM_0 core(PS) to ARM_1 core(PS) via PL, and the same data has to be loopback from ARM_1 core(PS) to ARM_0 core(PS) via fpga(PL) core. Kindly let me know how should i proceed for this. 

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