I am working with a USB-1608gx-2AO DAQ board and I am attempting to synchronize the TMR output with the analog outputs of the board. My goal is to generate an 11 kHz TTL pulse train from the TMR output at the same frequency as 11 kHz sine waves generated by the analog outputs on the board. To synchronize output of the TMR channel with the Analog output I have routed the Analog output clock to the TRG input on the board, and I have the TMR output to set to external trigger. This approach has worked to synchronize the output of the TMR with the AO on the board, however each time I stop and then restart my Python code the phase between the TMR TTL pulse train and the sine wave generated by the Analog output is different but they remain synchronized. I don't know if there is some kind of internal delay/latency on the DAQ board, or for some reason I am not triggering on the same part of the AOCLK pulse that I'm reading on the TRG input that is causing this run to run variation in phase between the signals.
If anyone has suggestions or a different recommendation for how to set-up the board to accomplish this task it would be much appreciated.
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bebrumfield123
Hi,
I am working with a USB-1608gx-2AO DAQ board and I am attempting to synchronize the TMR output with the analog outputs of the board. My goal is to generate an 11 kHz TTL pulse train from the TMR output at the same frequency as 11 kHz sine waves generated by the analog outputs on the board. To synchronize output of the TMR channel with the Analog output I have routed the Analog output clock to the TRG input on the board, and I have the TMR output to set to external trigger. This approach has worked to synchronize the output of the TMR with the AO on the board, however each time I stop and then restart my Python code the phase between the TMR TTL pulse train and the sine wave generated by the Analog output is different but they remain synchronized. I don't know if there is some kind of internal delay/latency on the DAQ board, or for some reason I am not triggering on the same part of the AOCLK pulse that I'm reading on the TRG input that is causing this run to run variation in phase between the signals.
If anyone has suggestions or a different recommendation for how to set-up the board to accomplish this task it would be much appreciated.
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