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DDR4 Memory direct Connection to FPGA on Zynq Ultrascale+ MPSoC Development Board


ConnorR

Question

My team was looking at purchasing the Genesys ZU: Zynq Ultrascale+ MPSoC Development Board. For our project, we need a direct connection (wired) between the DDR4 memory and the FPGA (i.e. no modules, controllers, chips, etc. in between). From looking at the documentation we think it is a direct connection but are not 100% sure. Any help verifying this before buying the board would be great! Thanks!

 

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Hi @ConnorR

Welcome to the Forums.

According to this quote from the Genesys ZU reference manual's Main Memory section, the DDR4 memory is connected to the Zynq PS, not the PL.

Quote

Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller.

This can also be seen in the schematics, where DDR-related nets are connected to bank 504. Page 27, here: New Output (digilent.com).

Hope this helps,

Arthur

 

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