Eclypse Z7 Zmods Block Diagram Integrated with Verilog Module

[Henry Walker]

Hi everyone, sorry if this is a very basic question, but I'm having trouble with creating a program for the Eclypse Z7 fitted with the Zmod ADC1410 (Scope).

In a nutshell, I ultimately want to have an Eclypse Z7 board fitted with two Zmod Scopes so I can concurrently sample four channels from my PCB. I intend to then feed the Zmod readings into a Verilog module which will create a circular buffer for each channel and then find the maximum and minimum values in said buffer to be then used in C++ (via Xilinx SDK). I am trying to implement this in Verilog so that I can best utilise the parallel programming capabilities of the Programmable Logic (instead of creating multiple threads in the Processing System).

My problem is that I am very inexperienced with handling IP blocks, so I am very unsure on how I can 'extract' the readings in each channel to be used in my Verilog module and subsequently send out the Verilog outputs to be used in the Processing System side. I have been heavily referencing the sample ADC/DAC project from Digilent's GitHub (https://github.com/Digilent/Eclypse-Z7/tree/zmod_adc_dac/master) as well as this sample from Hackster.io (https://www.hackster.io/whitney-knitter/hello-zmods-on-the-eclypse-z7-99107d). Unfortunately, I do not know how to modify the Block Design to get what I need.

Am I supposed to feed for example the output of the xlslice_chX blocks into my Verilog module as inputs and then subsequently route the outputs of the module to the sChXIn ports of the AXI_ZmodADC1410_X block (perhaps with some data controlling function within the module itself so I can send out the two output values in a single channel)? The provided block diagram is from the Hackster.io page.

Do I then need to do any special adjustments on the SDK as well, or would it be fine to just keep it as the sample project's with the AXI addresses?

I am using Vivado and Xilinx SDK 2019.1.

I will greatly appreciate any input and advice on this matter.

Many thanks in advance!

 

[artvvb]

Hey @Henry Walker

If you did implement the design using a separate RTL module between the AXI controller and low-level controller, I'd look at sending your min/max values up to the software via separate outputs connected to an AXI GPIO, while still forwarding all data passed into your module to the AXI controller, to continue using it for the bulk of the data transfer.

That said, while the idea of adding extra hardware to the block diagram in between the low-level controller and AXI controller is a good one - it's an easy place to get access to a new sample per channel every cycle - I think you should consider modifying the sources of the AXI controller (right click on it and "edit in IP packager". It already has a circular buffer to store a window of samples around a trigger event, which are then forwarded up to the processor. Actively iterating over the buffer contents to calculate mins and maxes as a separate step that blocks the software and other hardware from doing other things is likely to be slower than just doing the same step in software after data is received into DDR memory, since the processor clock is just faster than the PL clocks. I'd look at doing the calculations while the hardware is iterating over the buffer for other reasons, like when it's sending captured data to the DMA to be transferred up to DDR. This would also conveniently only look at the data inside of the trigger window, unlike hardware placed between the AXI and low-level controller.

The AXI controller also has an AXI interface that you could add a couple of extra register addresses to, that when read, could reply to the processor with calculated min/max values per channel. Alternatively, you could tack the calculated min/max values onto the end of the stream of data going from the AXI controller to the DMA. Either way, some software changes are required - extra register reads if doing the AXI interface, or an increase in the number of words read over DMA if extending the transfer (while taking care not to exceed the maximum buffer length that can be transferred).

Hope this helps,

Arthur