Reduce the sample rate of ADC

[youxuan]

Hi,I have some questions about FPGA.

Our development board is Eclypse Z7, and the ADC is Zmod ADC 1410. The environment we are using is VITIS 2019.1. From the official website, we know that the maximum sample rate of the ADC is 100MSPS. Due to our project requirements, we need to lower the sample rate of the ADC. We already know that the sample rate = number of samples / sampling interval time. Originally, we directly reduced TRANSFER_LEN to lower the number of samples, indirectly reducing the sample rate. However, this is not what we want. We hope to directly lower the sample rate and then reduce the number of samples. I asked ChatGPT, and it suggested changing the Sampling Clock, but I couldn’t find any related practical steps online. What methods are available?

[artvvb]

Hi @youxuan

If I recall correctly, there's no decimation or modifiable clocks built into the 2019.1 demos, which means that reducing the transfer length doesn't reduce the sample rate - samples are still coming in every clock cycle, so you'd be seeing a reduced overall capture length with the same sample rate...

If you're just dividing the sample rate by an integer, you might add a new module/IP into the AXI stream between the low-level controller and AXI controller or DMA that only keeps every Nth sample and discards the rest (decimation).

Otherwise, you're looking at reducing the clock frequencies forwarded to the low-level controller IP (the sampling clock as mentioned). For the 2019.1 demos, please refer to the low-level controller user guide (https://github.com/Digilent/vivado-library/blob/zmod/v2/2019.1-2/ip/Zmods/ZmodScopeController/docs/ZmodScopeController.pdf) for information on its clocking requirements (there's a required relationship between the sampling clock and ADC input clock, for example). Also be aware that you may need to also handle some issues like moving data and handshake signals from the ADC_SamplingClock clock domain to whatever clock domain downstream IP are on (an AXI stream data FIFO would help here). For the "how" of actually changing clock frequencies in the tools, you're looking at changing the parameters of the IP generating the appropriate clocks, whether in the Zynq PS configuration or a clocking wizard, and potentially creating new clocks if needed.

Hope this helps,

Arthur