Sample rate divider with acqmodeRecord

[AlanB]

I'm trying to set up a Digital Discovery with Python to use DigitalIn/acqmodeRecord to get a constant stream of data (from inputs 24-31).  I have it set up such that I can use repeated calls to FDwfDigitalInStatus(), FDwfDigitalInStatusRecord() and FDwfDigitalInStatusData() to retrieve the samples and process them, and this seems to be OK at slower rates.  I'd like to increase the sample rates as high as possible.

I can use FDwfDigitalInDividerSet() to set a divider to the 800MHz clock.  If I use a divider of 800 I think I get the expected pattern back from my test input.  However, reading the divider value using FDwfDigitalInDividerGet() gives a value of 1.  If I try to vary the divider that I set, the rate of my test pattern doesn't seem to match the expected rate and the read-back rate of the divider is still 1.

It seems from the discussion in https://forum.digilent.com/topic/25184-problem-with-aquisition-mode-record that I can set dividers of 1, 2, 4, 8, 16, etc.  However, I'm sure that these aren't all valid for acqmodeRecord and reading data back while simultaneously capturing data.  What are the constraints for setting a divider, and how can I tell what divider is being used if FDwfDigitalInDividerGet() always returns 1?

[attila]

Hi @AlanB

The divider should be valid. The data streaming rate is limited by the USB bandwidth.
Here is an example with continuous record at 1MHz (/800) DigitalIn_Record_Continuous.py

[AlanB]

Thanks for the response.

I've just discovered that FDwfDigitalInDividerGet() returns the expected value if I call it after starting the capture with FDwfDigitalInConfigure().

So I can keep turning down the divider value until I start seeing data being lost/corrupted in the call to FDwfDigitalInStatusRecord()?  (And then back off a bit to account for fluctuations in USB traffic on my bus!).

Is there any compression applied to the data in transit over USB?  Or can I expect the same results from a static signal as with a rapidly changing signal?

[attila]

Hi @AlanB

Probably you are using the recommended disabled autoconfigure:

For other devices I added data compression, but unfortunately the Digital Discovery FPGA is kind of full. I would have to reduce or remove some existing device features to add compression.