Need help understanding Basys3 FDV301N transistor circuit

[MBondaruk]

Hello

I am trying to implement a similar power sequence scheme as in Basys in a custom PCB of mine for a bigger Artix-7 chip.

My concern is what is the purpose of FDV301N transistor on page 8 of the public schematic revision D. It's base seems to be tied to RUN2 of LTC3633. RUN2 is an input so what exactly is supposed to enable the 3.3V rail in this circuit?

Sincerely,
Maksim Bondaruk

[asmi]

Artix-7 doesn't really care about power sequencing, I always ramp up all power rails at the same time, and never had any problems. See attached schematics of my A100T board with SODIMM for reference. The only rails which are delayed are MGT-related rail AVTT 1.2 V (because it's generated from 1.8 V rail) and auxiliary DDR3 ones - DDR3 VREF 1.5 V and DDR3 VTT 0.75 V - because likewise it's generated from the main DDR3 power rail.

A100 484 SODIMM Min Rev B2.pdf

[artvvb]

Hi @MBondaruk

I asked the design engineer for the Basys 3 - the Q4/Q5 circuit is there to discharge the bulk capacitance on the 3.3 V rail, helping make sure it's low at the start of the startup sequence, even if the board was only recently powered off.

Hope this helps,

Arthur

[MBondaruk]

21 hours ago, artvvb said:

Hi @MBondaruk

I asked the design engineer for the Basys 3 - the Q4/Q5 circuit is there to discharge the bulk capacitance on the 3.3 V rail, helping make sure it's low at the start of the startup sequence, even if the board was only recently powered off.

Hope this helps,

Arthur

Okay. One more question about the LTC3633 circuit. It seems that at the PHMODE pin INTVCC and GND seem to be shorted together through the 0 ohm resistances and that is unacceptable according to the LTC3633 datasheet?

Edited September 7 by MBondaruk