Since 2 days ago, synthesis fails in Vivado 2023.2 with the following error:
[Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file ......../Zybo-Z7-20-HDMI-hw.xpr/hw/hw.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
Not sure what makes it suddenly fail consistently, maybe an IP update in ILA ?
Question
Eran Zeavi
Hi,
I have successfully synthesized , run implementation, generate bitstream and run the demo on the Zybo-20 for months.
https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi?srsltid=AfmBOop9a-MucVEfknyx8HaKfWE7-R2OmdNU_QDW0KVyIGjC0MkbEdho
Since 2 days ago, synthesis fails in Vivado 2023.2 with the following error:
[Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file ......../Zybo-Z7-20-HDMI-hw.xpr/hw/hw.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
Not sure what makes it suddenly fail consistently, maybe an IP update in ILA ?
Any idea ?
Thans
Eran
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