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Zybo Z7 HDMI Input/Output Demo - new issue in Vivado


Eran Zeavi

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Hi,

I have successfully synthesized , run implementation, generate bitstream and run the demo on the Zybo-20 for months.
https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi?srsltid=AfmBOop9a-MucVEfknyx8HaKfWE7-R2OmdNU_QDW0KVyIGjC0MkbEdho

Since 2 days ago, synthesis fails in Vivado 2023.2 with the following error:

[Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file ......../Zybo-Z7-20-HDMI-hw.xpr/hw/hw.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

Not sure what makes it suddenly  fail consistently, maybe an IP update in ILA  ?

Any idea ?

Thans

Eran

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Hey @Eran Zeavi

Apologies for the delay. What release download are you using? We can generally only support demos in the version that they're built for, but I'm not aware of any substantial changes on the Vivado side from 2023.1 to 2023.2 that would cause issues (Vitis on the other hand...).

Is the ila_pixclk message an error or a warning? Could you forward any other errors or warnings you're seeing? The constraint file referenced should be related to an internal logic analyzer module that can be optionally instantiated in the rgb2dvi core - I'm assuming that it's disabled in the project.

Thanks,

Arthur

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I am using the 2024 version of the demo with Vivado 2024 for Windows. The demo has been synthesizing and running just fine for months. Since 3 weeks ago, I am experiencing recurrent and random  crashes of Vivado during "generate block design" and I have synthesis generating a blank "synthesized  Design". Reinstalling Vivado-2024 for Windows from scratch did not help. Reverting last Windows updates did not help; reinstalling JAVA did not help. I have systematic Vivado crashes or failing synthesis at best.
ila_pixclk message is a warning but synthesis fails.
Not sure how to go from there ...

Pictures attached to illustrate the issue.

Thanks for the help !

Capture.JPG7.JPG

Capture.JPG6.JPG

Capture.JPG5.JPG

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no error, just critical warnings on refclk and pixclk modules not found 

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

INFO: [Timing 38-2] Deriving generated clocks [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of [get_ports -scoped_to_current_instance clk]'. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2]
Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2]
CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:5]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:6]

 

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No issues with rebuilding the bitstream for me, and I see all the same warnings. Have you tried redownloading the ZIP file to start fresh?

image.png

I assume you have the ILA disabled (as in the "debug module" option unchecked, as below)?

image.png

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not able to build any other project.
I ll probably upgrade to windows 11 since it's working for you . A Windows 10 update may have killed my environment and would not be surprised ...
Is Vivado working on VM too ? Ubuntu VM for instance ?


Thank you though for the help !

 

Edited by Eran Zeavi
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1 minute ago, artvvb said:

I haven't personally tried 2024.1 in a VM yet, and it's been some time since the last time I did for an older version. I believe Whitney Knitter uses a non-virtual Ubuntu OS successfully - this guide might be helpful: Vivado, Vitis, & PetaLinux 2024.1 Install on Ubuntu 22.04 - Hackster.io.

Sounds good thanks !

 

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