Are there any example for HDMI => VGA converter that VGA reasult stored on BRAM also

[tuan]

Dear everybody.

Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO.

I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use.

PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet.

As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM.

I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose.

Best Regards,

[tuan]

On 11/8/2016 at 11:00 PM, jamey.hicks said:

Zybo only has 230KB of BRAM. If the images fit in BRAM you should be able to use it.

There is also 256KB of OCM, but there are not many reference designs out there that use it.

Most likely, you will need to capture frames in DRAM.

 

Dear everybody

Dear jameu.hicks

Thank you very much for your reply and sorry for my late feedback.

I have a mistake in my first post. We need to read RGB data generated from HDMI input, and so DRAM is also good to me.

I found a design in Japan which write RGB data to vram via AXI bus so that other module can read and show on display while PS also can access to this data.

However I have timing violation problem in synthesis and implementation, that is hold time and setup time violation occur between registers belong to different clock domain (74.25MHz for DVI and 200MHz for PS and also AXI bus for writing converted RGB data to vram). Also, setup time problem occurs inside AXI interconnect module (working at 200MHz).

Setting false path among those clock domain causes data enable signal between those 2 domains takes 0 in all the time, and so no data is written into vram. This problem does not happen in reading module (via the AXI interconnect working at 200MHz above).

I also tried to make register among different domain locates close to the other by using plan ahead, setting the ASYNC_REG attribute on the flip-flops in the synchronize but non of them works. Do you have any way to solve the timing violation in this case?

Best Regards,

 

 

[D@n]

@tuan,

Welcome to one of the more difficult problems in FPGA design! 

I think you will find that Cliff Cummings wrote an excellent article on how to move from one clock domain to another.  He not only describes the problem of metastability, but also provides many strategies for handling it.  In your case, I think you will find that writing to a FIFO with one clock, and then reading it out with the other clock once half the FIFO has filled might be just the thing you are looking for.

Dan