Error During Run implementation of vivado Project

[Muhammad Ahmad]

Hi everyone,

i am trying to make a project in which i am using zedboard and vivado 2018.2. i am trying to make a project in which we can generate a clock frequency of 20MHz from pmodA and then this is given to PCB board and the PCB returns 3 outputs which is given to PmodB and i want to show their result. Can anybody help m regarding this. i am facing an error.

[DRC REQP-1712] Input clock driver: Unsupported PLLE2_ADV connectivity. The signal design_1_inst/design_1_i/clk_wiz_0/inst/clk_in1 on the design_1_inst/design_1_i/clk_wiz_0/inst/plle2_adv_inst/CLKIN1 pin of design_1_inst/design_1_i/clk_wiz_0/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
i am attaching block design diagram

[dpaul]

@Muhammad Ahmad

Please send out the clock from an ODDR macro, which sits within an IO block.

https://www.adiuvoengineering.com/post/microzed-chronicles-outputting-clocks

https://support.xilinx.com/s/question/0D52E00006hpcgDSAQ/why-oddr-for-forwarded-clock?language=en_US

 

 

[Muhammad Ahmad]

1 hour ago, dpaul said:

@Muhammad Ahmad

Please send out the clock from an ODDR macro, which sits within an IO block.

https://www.adiuvoengineering.com/post/microzed-chronicles-outputting-clocks

https://support.xilinx.com/s/question/0D52E00006hpcgDSAQ/why-oddr-for-forwarded-clock?language=en_US

 

 

@dpaul 

I didn't understand about your solution. which clock i have to send and where? 

basically when i am using clocking wizard then we setup it input to 100MHz and output to 20Mhz.

[dpaul]

20 hours ago, Muhammad Ahmad said:

i am trying to make a project in which we can generate a clock frequency of 20MHz from pmodA and then this is given to PCB board and the

THat means, you want to generate a clock which goes out of the FPGA through a Pmod pin.
 

16 hours ago, Muhammad Ahmad said:

basically when i am using clocking wizard then we setup it input to 100MHz and output to 20Mhz.

Till the above line your comment is correct. But you simply do not connect the 20MHz output of an MMCM/PLL to the Pmod pin.

 

How to do it in the right way, I have mentioned in my previous post. Please read the first link carefully. It tells you how to use an ODDR to output clock from an FPGA.