Arty Z7 DDR simulation problem

[wayyu]

Hello

 

I'm currently working on a project with a lot of access to DDR on my board, and I'm trying to run simulation to know if my design is work.

Since the there's a DDR controller inside the ZYNQ, I use MIG to generate a memory interface and use ddr module in it's example design, but the simulation result shows that the DDR module's signal is all Z.

So I'm wondering if there a way to just use my ZYNQ DDR configuration to generate a ddr module for simulation?

Or did Digilent provide ddr module or MIG configuration that matches my board.

Thanks everyone!!!

[artvvb]

Hi @wayyu

Apologies for the delay. The Arty Z7 does not make use of the MIG for DDR, as the DDR memory is connected to the Zynq PS hard DDR controller instead of Zynq PL (FPGA fabric). The Zynq PS core is configured with the correct timing information when you use its board files in your project and run block automation, as described in this guide: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi. I don't have resources to provide on simulating the Zynq PS - you may find some material about it on AMD's website.

Thanks,

Arthur