Adding MMCM/PLL to a project

[trossin]

When using Vivado (2023.2), if I use the Clocking Wizard from the IP catalog (under FPGA Features and Design) to add the MMCM/PLL to my project it seems to add it under sources.  But, when I click Run Synthesis, it does not find the wrapper file clk_wiz_0_clk_wiz.v and fails.  So, I just manually add it to sources as it exists down at ProjectName.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v.  Now the project will compile but gives me a warning about this file has been included twice.  Ugh.

Is this normal or is there some secret that I missed?

[dpaul]

@trossin

So after you have added the MMCM from Clocking Wizard, it is added to your Project but is is NOT connected to your design.

You need to instantiate the added MMCM to your design and connect the signals to work further.

Have you already done the above?

[trossin]

Yes. I already instantiated the MMCM after using the clock wizard and saw it was added to the project. But when I went to build the project, it said it could not find the Verilog for the wrapper I instantiated. So, I found the code and manually added it. Then the project built and worked in HW but gave me a warning about the wrapper being added twice. 
 

I will try again from a blank project and try to repeat. If I can do that, I’ll try quitting after the first build error and reload the project and see if a reload allows the build to work without adding the wrapper manually. 
 

I will mention that I have had the tool crash on me a few times and I also accidentally start Vivado twice (takes a long time to show splash screen). I have found that certain operations fail or crash if I have a second instance running or the tool crashed and I did not reboot.  This might be my issue as the first time I used the clock wizard, it crashed during generation. Maybe it left a turd that won’t be around if I just try again. 
 

Thanks for your help. I’ll let you know how it goes. 

[artvvb]

Hi @trossin

You can find templates for instantiating IP cores in the IP Sources tab in Vivado:

Try instantiating clk_wiz_0 instead of clk_wiz_0_clk_wiz.

Thanks,

Arthur

[trossin]

Thanks Arthur,

This worked:

    clk_wiz_0 MmcmPllThing( 
         .clk_out1(Clk)
        ,.locked(Locked)
        ,.clk_in1(RefClk)
    );

Your screen shot made me think I had to connect 20 signal so I freaked out at first.  Now I see that clk_wiz_0 is above clk_wiz_0_clk_wiz in the hierarchy so I should have inserted that into my design instead.  Thanks for the help.

 

[artvvb]

Apologies for the moment of panic there - I had the AXI interface enabled to modify some MMCM settings while this particular project is running on a board. Different settings for different projects. The template in your project should work for your settings. Loading up a second clocking wizard, this is what the template for default settings looks like for me: