Cmod A7-35 PLL power on reset?

[trossin]

So I looked around and see that there is no power on reset for this module that can be used by internal logic. I've used a board with a Lattice FPGA that also didn't have a power on reset but like this device will initialize all flops to zero when the programming is done.  On the lattice board, I just created a counter on the reference clock that counts up to 20 and while counting asserts reset into the PLL.  I then used this reset and the locked output from the PLL and more synchronizing flops on the PLL output clock to generate a system reset which is required for 1 hot state machines to work.

I thought I would do the same thing with the Vivado tools but the synthesis tool got pissy about putting flops on the same clock as the reference clock to the MMCM/PLL so that does not work.  What I did was tie the MMCM/PLL reset to zero and just use the locked output to generate my reset and things worked.

Did I get lucky or is this the recommended way to generate a power on reset?

P.S. I found that the built in simulator ignored my inital/begin code to set my little counter to zero.  Icarus was able to simulate it correctly (and gets me results quicker so I stick with that until I need the built in simulator for some other reason like IP modeling). 

[trossin]

I guess I'm answering my own question.  I now see that the reset input is an optional port to the MMCM so I created another project and unselected the reset port and it works fine.  Just a clock in, clock out and locked signal.  I can make the reset using the locked signal.  All is good.

Here is my source that converts the 12 MHz clock into 100 MHz to flash the LEDs (I should have more flops on nRst but it is just an example):

 

module Fun(
     input  RefClk
    ,output[1:0] Led
    ,output[2:0] nRgb
);
    wire Por,Clk,Locked;
    reg[21:0] Counter;
    reg[2:0] Count;
    reg CountEn,nRst;
    
    clk_wiz_0_clk_wiz MmcmPllThing( 
         .clk_out1(Clk)
        ,.locked(Locked)
        ,.clk_in1(RefClk)
    );
    
    assign Led = Count[1:0];
        // 50% duty cycle as it is too bright
    assign nRgb = Counter[15] ? Count : 7;

    always @(posedge Clk) begin
        nRst <= Locked;
        Counter <= (~nRst) ? 0 : Counter + 1;
        CountEn <= Counter==1 ? 1 : 0;
        Count <= (~nRst) ? 0 : CountEn ? Count+1 : Count;
    end
endmodule