I'm trying to use the HDMI ports to input a live camera feed into the input and then transmit it through the output port to a monitor. I followed this video for the design and it seemed very simple.
I've seen the demo that is associated with the HDMI arty z7 set up but couldn't get it working, its not exactly what i need and it was somewhat out dated so I had trouble following.
Anyways I'm having a lot of trouble getting this going and i feel like it should be pretty straight forward based of the video i watched so i wanted to see if anyone can help out/ get a second pair of eyes on the situation. Thanks in advance.
Errors I encountered:
one major problem i had was with the dvi2rgb IP block. When i first put it in the block design vivado said it was configured for the Arty z7 -10 but there was no way to change it and my project was set up for Arty Z7 -20 before i placed any IP blocks. Then, using the linter, i got the errors shown below. The ip wasnt able to read dgl_720p_cea.data so I copied it and put it in the exact folder that EEPROM_8b was so that EEPROM_8b could read it because that was the file that was referencing dgl_720p_cea.data. After doing that, the linter worked with no errors but if i touch the block design i made that contains the IP blocks it will delete the dgl_720_cea.data from the folder i copied it to and the linter will once again output the errors below.
ERROR: [Synth 8-3302] unable to open file 'dgl_720p_cea.data' in 'r' mode [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/EEPROM_8b.vhd:90]
ERROR: [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/EEPROM_8b.vhd:115]
Question
woj
Im using an ARTY z7-20 and vivado 2024.1
I'm trying to use the HDMI ports to input a live camera feed into the input and then transmit it through the output port to a monitor. I followed this video for the design and it seemed very simple.
https://www.youtube.com/watch
I've seen the demo that is associated with the HDMI arty z7 set up but couldn't get it working, its not exactly what i need and it was somewhat out dated so I had trouble following.
Anyways I'm having a lot of trouble getting this going and i feel like it should be pretty straight forward based of the video i watched so i wanted to see if anyone can help out/ get a second pair of eyes on the situation. Thanks in advance.
Errors I encountered:
one major problem i had was with the dvi2rgb IP block. When i first put it in the block design vivado said it was configured for the Arty z7 -10 but there was no way to change it and my project was set up for Arty Z7 -20 before i placed any IP blocks. Then, using the linter, i got the errors shown below. The ip wasnt able to read dgl_720p_cea.data so I copied it and put it in the exact folder that EEPROM_8b was so that EEPROM_8b could read it because that was the file that was referencing dgl_720p_cea.data. After doing that, the linter worked with no errors but if i touch the block design i made that contains the IP blocks it will delete the dgl_720_cea.data from the folder i copied it to and the linter will once again output the errors below.
ERROR: [Synth 8-3302] unable to open file 'dgl_720p_cea.data' in 'r' mode [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/EEPROM_8b.vhd:90]
ERROR: [Synth 8-421] mismatched array sizes in rhs and lhs of assignment [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/EEPROM_8b.vhd:115]
ERROR: [Synth 8-285] failed synthesizing module 'EEPROM_8b' [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/EEPROM_8b.vhd:85]
ERROR: [Synth 8-285] failed synthesizing module 'dvi2rgb' [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ipshared/f99d/src/dvi2rgb.vhd:112]
ERROR: [Synth 8-285] failed synthesizing module 'design_1_dvi2rgb_0_0' [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/synth/design_1_dvi2rgb_0_0.vhd:81]
ERROR: [Synth 8-285] failed synthesizing module 'design_1' [c:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/synth/design_1.vhd:40]
ERROR: [Synth 8-285] failed synthesizing module 'design_1_wrapper' [C:/Users/matty/Downloads/Seniorproject/HDMI6-10/HDMI6-10.gen/sources_1/bd/design_1/hdl/design_1_wrapper.vhd:32]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 4155.422 ; gain = 0.000
---------------------------------------------------------------------------------
HDMI6-10.xpr EEPROM_8b.vhd dgl_720p_cea.data
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