Upgraded to Version 2024.1 of Vitis and cannot debug Application

[PerseusIII]

I have the Arty S7-50 evaluation board and recently upgraded to version 2024.1 of the Xilinx tools.  I created a simple project using your 'Getting Started with Vivado and Vitis for Baremetal Software Projects'.  However, when I got to the point of running and debugging the Hello World application, I get a connection error from Vitis.  Below is the output from the Vitis Server.  I've also attached a screen shot from the pop up window describing the error.  Is this a Digilent problem or a Xilinx one?  Any help would be appreciated.

 

13:44:13 INFO  : connect -url tcp:127.0.0.1:3121

13:44:19 INFO  : 'targets -set -filter {jtag_cable_name =~ "Digilent Arty S7 - 50 210352B7DF22A" && level==0 && jtag_device_ctx=="jsn-Arty S7 - 50-210352B7DF22A-0362f093-0"}' command is executed.

13:44:20 INFO  : Device configured successfully with "C:/Work/Xilinx/Workspace/Projects/MCPv2/Hello/_ide/bitstream/System_wrapper.bit"

13:44:26 ERROR : Error in selecting the processor

 

Edited June 7 by PerseusIII
Put wrong version number in title

[artvvb]

Hey @PerseusIII

We don't have much experience with 2024.1 yet, and that guide has not been updated for it - there are some fairly large changes in the Vitis UI between 2023.1 and 2023.2. Do you need to use 2024.1, or would you be able to revert to an older version? Anecdotally, 2023.1 feels pretty stable.

For your specific question, I'm not sure. We'll need to do further testing to try to replicate your issue. Could you try programming the FPGA separately before running the software app? In older versions (the "Vitis classic" UI) there's usually an option to do it, like Vitis -> Program Device in the top menus.

Thanks,

Arthur