Nexys 4 DDR confused in setting the appropriate clock period in MIG to access ddr2 memory

[stealth sniper]

Hello! I am newbie with FPGA, and I am trying to utilise the DDR2 memory on the nexys 4 DDR board. Based on Digilent's website, the clock period for the ddr2 memory is 300Mhz, and the reference clock should be set to "Use system clock". However, to enable t he "Use system clock" option in the Memory Interface Generator, my input clock period has to be set to 200Mhz instead of the 300Mhz of what the website has said. What should i do here? Am I suppose to match the input clock period of the MIG with the clock period of the memory?

 

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[Viktor Nikolov]

Perhaps this tutorial will help you. I created it to show how to use DD3 memory with the Microblaze soft CPU. Nevertheless, the MIG configuration part is also valid for designs without the Microblaze.
The tutorial uses the Arty A7 board, but the steps should also work on Nexys.

In short: You must connect the 100 MHz system clock to the MIG.sys_clk_i via BUFG Utility Buffer. You must have a Clocking Wizard to generate 200 MHz and feed it to MIG.clk_ref_i.
This is because, for technical reasons of the MIG, sys_clk_i must come from an external oscillator (not an internal Clocking Wizzard), and clk_ref_i must be precisely 200 MHz.
I describe the details here.

[stealth sniper]

2 hours ago, Viktor Nikolov said:

Perhaps this tutorial will help you. I created it to show how to use DD3 memory with the Microblaze soft CPU. Nevertheless, the MIG configuration part is also valid for designs without the Microblaze.
The tutorial uses the Arty A7 board, but the steps should also work on Nexys.

In short: You must connect the 100 MHz system clock to the MIG.sys_clk_i via BUFG Utility Buffer. You must have a Clocking Wizard to generate 200 MHz and feed it to MIG.clk_ref_i.
This is because, for technical reasons of the MIG, sys_clk_i must come from an external oscillator (not an internal Clocking Wizzard), and clk_ref_i must be precisely 200 MHz.
I describe the details here.

I have read your tutorial, and it very good! However, there some issues I have encountered while reading it. Firstly, where does "MIG.clk_ref_i." suddenly comes from? Secondly, the link to the  UG586, (page 210) is no longer working.

Edited May 31 by stealth sniper

[DAQman]

"MIG.clk_ref_i." looks like a type-o that should have been written as "the MIG clk_ref_i input terminal."

Thanks for the heads-up on the broken link. 

[Viktor Nikolov]

Thanks for pointing out broken links to UG586. Guess what? They published a new version of UG586 yesterday.
I fixed the links in the tutorial.

The notation "MIG.clk_ref_i" was meant to resemble C/C++ notation <structure>.<element_of_the_structure> .
I get it. It may be confusing. I updated the text so this notation is no longer used.

Thanks for the feedback. 👍

[stealth sniper]

15 hours ago, Viktor Nikolov said:

Perhaps this tutorial will help you. I created it to show how to use DD3 memory with the Microblaze soft CPU. Nevertheless, the MIG configuration part is also valid for designs without the Microblaze.
The tutorial uses the Arty A7 board, but the steps should also work on Nexys.

In short: You must connect the 100 MHz system clock to the MIG.sys_clk_i via BUFG Utility Buffer. You must have a Clocking Wizard to generate 200 MHz and feed it to MIG.clk_ref_i.
This is because, for technical reasons of the MIG, sys_clk_i must come from an external oscillator (not an internal Clocking Wizzard), and clk_ref_i must be precisely 200 MHz.
I describe the details here.

By the way, I don't understand why even though the reference clock for Arty's setting is set to "No Buffer" while Nexys' is set to "use system clock", the connection should still remain the same. Like, i read the documentation and it sort of didn't explain what the options do.

And I have also read the clocking architecture through the link you provided, I can't seem to connect the documentation's explanation to your implementation.
1) Why did they use IDELAY instead of just saying external clock?
2) What is PHY here refers to? As in, how do i know what module is a PHY? Is the PHY refers to the MIG?
3) "The MMCM compensates for the insertion delay of the BUFG to the PHY". Since we chose the "No buffer" option, we have to manually add back the BUFG right? Why can't we just use existing BUFG?
4) "one of the phaser frequency reference clocks runs at the same frequency as the memory clock and the second frequency reference clock must be either 2x or 4x the memory clock frequency". How does this related to the MIG's reference clock and system clock?

On the Arty A7 webpage, it says the maximum clock period is 3000ps. But if the ratio is now 4:1, does that mean our memory clock is now reduced by 4 times? Why does it needs to be set liek this?

 

Edited June 1 by stealth sniper

[Viktor Nikolov]

As you discovered by reading UG586, the Memory interface is pretty complicated under the hood of MIG. 🙂

The design I present in the tutorial is definitely not the only possible HW design.

However, my design was driven by a need to resolve the issue specific to Arty A7, Nexys A7, and other Digilent boards: The external 100 MHz oscillator is connected to pin E3 in Bank 35. Bank 35 is powered to 3.3 V, and MIG, for some reason, expects sys_clk_i to be a 2.5 V signal.
That's why I introduced BUFG and disabled the System Clock buffer in the MIG configuration; otherwise, various errors would have arisen during implementation.

I wasn't aware that on Nexys, the MIG also shows the option "Use System Clock" for the Reference Clock (it doesn't do so on Arty A7). I guess the board file for Nexys differs from Arty's.
However, using a system clock as a Reference Clock would be wrong. This is because UG586 clearly states that 200 MHz is needed for the Reference Clock for DDR2/DDR3, but Nexys only has a 100 MHz external oscillator to provide the system clock.

PHY refers to the Physical Layer of the Memory Interface; see Figure 21.

I believe IDELAY is a concept in digital signaling for DDR3 (but I'm not an expert on this). MIG needs a 200 MHz Reference Clock for IDELAY control.

"MMCM" probably refers to an MMCM shown in the figure in the UG586 in the chapter Clocking Architecture.

Quote

On the Arty A7 webpage, it says the maximum clock period is 3000ps. But if the ratio is now 4:1, does that mean our memory clock is now reduced by 4 times? Why does it needs to be set liek this?

Yes, that's right. In this case, the physical layer will run at 81.25 MHz. The very same frequency is also used for MIG's AXI Slave Interface, which runs on the clock ui_clk coming from the MIG.
81.25 MHz is obviously not a super-fast memory. If speed is of the essence, use block RAM on the FPGA (Block Memory Generator IP).

Edited June 1 by Viktor Nikolov

[stealth sniper]

May I know how do you READ and WRITE data to and from the Microblaze and DDR memory? Like, what are the ports that is needed to be connected based on your tutorial. I would like to write my own c program to read and store data in the DDR but i dont know how. It's so confusing! 
Also, is there another way I could contact you for further questions? (If you okay with it) Thanks!!

Quote

Yes, that's right. In this case, the physical layer will run at 81.25 MHz. The very same frequency is also used for MIG's AXI Slave Interface, which runs on the clock ui_clk coming from the MIG.

If you mean the RAM's AXI interconnect, the 81.25Mhz is actually connected to the Master port (M00_aclk) though. The S00_aclk is connected to 100MHz

Also, why don't the order matter?
Why does the M_axi_DP is not connected to the ram_interconnect? Why is it connected to the peripheral AXI? How are you sending data in and out of the memory from the processor? I also cant seem to understand the difference between cached memory and non-cached memory. Like, does how does non-cached work? I read so many forums yet i still cant understant it

 

Edited June 1 by stealth sniper

[Viktor Nikolov]

The result of my tutorial is an HW design that allows you to run the programs on the Microblaze CPU. It will use DDR SDRAM as the memory. When MIG is present in the design, Vitis will compile and link the program to use the DDR SDRAM (unless you make changes to the default setting).

In my design, all AXI Interconnect interfaces toward the Microblaze run at 200 MHz, i.e., on the Microblaze's frequency (100 MHz can be used as a conservative setting). ram_interconnect's AXI interface towards MIG has to run at 81.25 MHz ui_clk coming from the MIG; this is the bottleneck.

I suggest you check the description of Microblaze AXI Interfaces here. Usually, you use the same RAM for instructions and data. Therefore, M_AXI_DC and M_AXI_IC go to a single AXI Interconnect. The order in which you make connections doesn't matter to the AXI Interconnect.

For performance reasons, it's better to have a dedicated AXI Interconnect to connect to the RAM. That's why M_AXI_DP has its own interconnect.

Microblaze will use data and instruction cache if you configure it that way. FPGA block RAM is used as a cache. I recommend always using caches with the Microblaze.
But you must enable the use of caches in the code. It is not enabled automatically. You place the commands at the start of your program:

#include "xil_cache.h"

int main() {
	Xil_ICacheEnable();
	Xil_DCacheEnable();
	
	// ...
}

[stealth sniper]

2 hours ago, Viktor Nikolov said:

Therefore, M_AXI_DC and M_AXI_IC go to a single AXI Interconnect. The order in which you make connections doesn't matter to the AXI Interconnect.

For performance reasons, it's better to have a dedicated AXI Interconnect to connect to the RAM. That's why M_AXI_DP has its own interconnect.

But by the looks of the diagram, only M_AXI_DC and M_AXI_IC have direct connection to the DDR memory, while M_AXI_DP doesnt. Which of these lines are the one that is responsible for the read and write to the memory though? Isnt it (S0_AXIS..S15_AXIS) and (M0_AXIS..M15_AXIS) used to stream the data to the RAM?

And whats the function of the connection of the DP connecting to the UART and GPIO? Can't i just connect to lets say simple LED without using any of these?

 

2 hours ago, Viktor Nikolov said:

The result of my tutorial is an HW design that allows you to run the programs on the Microblaze CPU. It will use DDR SDRAM as the memory. When MIG is present in the design, Vitis will compile and link the program to use the DDR SDRAM (unless you make changes to the default setting).

WOW! I see! Hmm..let's say I want to build a matrix multiplication engine that can write and read data from the DDR ram, do I still need to build the Matrix multiplication hardware in verilog? I wonder if the microblaze is even neccessary to read and write data to and from the DDR ram. I also wonder if I just build the engine in verilog separately have it processed  by that instead of being processed by microblaze.

I read so many documentation and I can't seem to solve my confusion for some reason. How did you even figure out how to build this? Like even when I look at these, i cant seem to understand and build them

 

[Viktor Nikolov]

Let's take a step back. 🙂

What do you need to build?

Matrix multiplication engine? Why use FPGA? For possible performance benefits?
How do you plan to get data in and out?