I remain puzzled at why my AXI QSPI block doesn't seem to work. I appreciate the effort Xilinx put into developing the driver files for much of their IP blocks and in general, I understand and like the parallel structure they seem to use across them, but I think they've often made them unnecessarily complicated, and the documentation could certainly be improved. My debugging efforts have yet to actually see data transferred on the SPI bus.
So I figured I'd take a step in a different direction and use one of the SPI blocks from the Zynq IP to see an actual working SPI implementation.
If I enable SPI 0, for example, there are a few options for the pins that can be used. Looking at the Zybo-10 schematic, the MIO 16..21 (ENET 0), 28..33 (USB 0), and 40..45 (SD 0) pins are all connected directly to the mentioned peripherals, so they don't seem to be able to be used for my test purpose. That leaves EMIO as the only available option. But... I don't know how to route EMIO to output ports in the Vivado design. If this is even possible, does anyone have a doc or example they could point me to, please?
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engrpetero
I remain puzzled at why my AXI QSPI block doesn't seem to work. I appreciate the effort Xilinx put into developing the driver files for much of their IP blocks and in general, I understand and like the parallel structure they seem to use across them, but I think they've often made them unnecessarily complicated, and the documentation could certainly be improved. My debugging efforts have yet to actually see data transferred on the SPI bus.
So I figured I'd take a step in a different direction and use one of the SPI blocks from the Zynq IP to see an actual working SPI implementation.
If I enable SPI 0, for example, there are a few options for the pins that can be used. Looking at the Zybo-10 schematic, the MIO 16..21 (ENET 0), 28..33 (USB 0), and 40..45 (SD 0) pins are all connected directly to the mentioned peripherals, so they don't seem to be able to be used for my test purpose. That leaves EMIO as the only available option. But... I don't know how to route EMIO to output ports in the Vivado design. If this is even possible, does anyone have a doc or example they could point me to, please?
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