I am try to test Xilinx MIPI CSI2 Rx Subsystem IP using FMC Pcam Adapter with Genesys2 FPGA board. I have problems with high-speed data and clock signals. While tracing the root cause, I found that the the high speed clock/data MIPI signals on FMC connector LA01_P, LA10_P, LA06_P are connected to Bank 16 of the XC7K325T-2FFG900 (FPGA chip on Genesys2)package pins D26, D29, and B27. Unfortunately, Bank 16 is HR (not HP) bank and does not support internal termination and Genesys2 board does not have external termination resistors on these pins. Without proper termination, FMC Pcam Adapter + Pcams won't work reliable on Ge
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I am try to test Xilinx MIPI CSI2 Rx Subsystem IP using FMC Pcam Adapter with Genesys2 FPGA board. I have problems with high-speed data and clock signals. While tracing the root cause, I found that the the high speed clock/data MIPI signals on FMC connector LA01_P, LA10_P, LA06_P are connected to Bank 16 of the XC7K325T-2FFG900 (FPGA chip on Genesys2)package pins D26, D29, and B27. Unfortunately, Bank 16 is HR (not HP) bank and does not support internal termination and Genesys2 board does not have external termination resistors on these pins. Without proper termination, FMC Pcam Adapter + Pcams won't work reliable on Ge
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