Getting error while making "pmod out" pin external of TMP3 on vivado 2016.1

[Manan Joshi]

I am using Zynq ZC702 board for this project, also this is my first time using pmod sensor.

getting this critical warning while adding ip:

create_bd_cell -type ip -vlnv digilentinc.com:IP:PmodTMP3:1.0 PmodTMP3_0
CRITICAL WARNING: [BD 41-51] Could not find bus definition for the interface: Pmod_out
CRITICAL WARNING: [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
endgroup

Getting this error while applying external connection to the "pmod out" pin:

ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.

Do i need to individually out every single out pins or either the ip is not compatible with vivado 2016.1?

Edited April 27, 2023 by Manan Joshi
forgot to add the board details.

[artvvb]

Hi @Manan Joshi, welcome to the forum!

Not sure if the IP will work in 2016.1 or not, we haven't tested it in that version any time recently, if at all.

When adding vivado-library to your project as an IP repository, did you choose the "IP" folder inside of vivado-library, or did you choose "vivado-library" itself? That's one way that the interfaces folder, "if", might not get detected by your project. That folder is where the interface definition for Pmod_out resides.

Thanks,

Arthur

[Manan Joshi]

14 hours ago, artvvb said:

Hi @Manan Joshi, welcome to the forum!

Not sure if the IP will work in 2016.1 or not, we haven't tested it in that version any time recently, if at all.

When adding vivado-library to your project as an IP repository, did you choose the "IP" folder inside of vivado-library, or did you choose "vivado-library" itself? That's one way that the interfaces folder, "if", might not get detected by your project. That folder is where the interface definition for Pmod_out resides.

Thanks,

Arthur

hello @artvvb, thanks for reaching out.

I had accidently add just the "pmods" folder instead of vivado_library folder. So the pmod_out issue has been rectified & thank you for pointing out the mistake.

Also i had another query if you please don't mind. I have completed the block design and also synthesized the design, now when i open the synthesized design for i/o planning the Pmod_out_8473 is showing 8 scalar ports which need to be assigned. Now i have checked in the schematic file of zc702 there aren't 8 pmod ports. would you please help me out with this if you can.

 

[artvvb]

No problem!

Referring to the ZC702 datasheet, particularly "User PMOD GPIO Headers" starting on page 49, it looks like you may need to wire the Pmod to the eight Pmod1_# and Pmod2_# pins using some additional cabling, as there isn't a full 2x6 connector with FPGA-connected IO.

Thanks,

Arthur

[Manan Joshi]

On 4/28/2023 at 11:37 PM, artvvb said:

No problem!

Referring to the ZC702 datasheet, particularly "User PMOD GPIO Headers" starting on page 49, it looks like you may need to wire the Pmod to the eight Pmod1_# and Pmod2_# pins using some additional cabling, as there isn't a full 2x6 connector with FPGA-connected IO.

Thanks,

Arthur

@artvvb hello arthur once again thank you for helping me out. I have done the pin mapping on the J63 & J62 PMOD headers after which i was able to generate the bitstream successfully. 

Another problem which i am facing right now is after writing the code in SDK and generating boot image. My sensor is reading -273.15 degree celsius, which i think is due to error in sdk code. if possible would you please help me out? I have attached the pin mapping photo & also the .txt file of the code.

Regards,

Manan Joshi

code.txt

[artvvb]

The xiicps driver is the driver for the Zynq PS's hard IIC controller rather than the soft-core AXI IIC used inside the PmodTMP IP. Drivers for the PmodTMP should be included in the hardware platform project, including example code. You should be including the "PmodTMP.h" header. It would also be possible to reconfigure the Vivado project to map a hard PS IIC controller to Zynq EMIO and connect it to the relevant Pmod pins, in order to save FPGA resources and use the xiicps driver, but that would potentially be more work than trying to use what you've already got. In that scenario, you'd also potentially need to map the other Pmod pins to EMIO GPIO or an AXI GPIO, and rewrite software found in the PmodTMP drivers.

Thanks,

Arthur