CMOD A7: PIO Bank Voltage Patch to 1V8

[DanielD]

Hi,

 

I want to attach an 1V8 DRVDD ADC to the CMOD A7 Board via the PIO pins. However all A7 PIOs are on VCC3V3.

 

To provide a 1V8 PIO I see two options:

1) Patch VCCO_35 and VCCO_16 to VCC1V8

2) Patch VCCO_34 to VCC1V8

 

Implementation of Option 1) would be:
- Cut VCC3V3 trace at C54 and C29

- Patch VCC1V8 from C82 to C54 and C29

Implementation of Option 2) would be:

- Cut VCC3V3 trace at C41

- Patch VCC1V8 from C82 to C41

Can you please tell me, if there is an appropriate place on the PCB to cut the VCCO_3V3 trace before C54, C29 and/or C41?

 

I saw other Forums entries discussing this. The most appropriate is [1] which gives hints to patch the Basys Board.

 

Thank you very much and best regards,

Daniel.

 

--

[1]

CMOD A7 Wiki: https://digilent.com/reference/programmable-logic/cmod-a7/reference-manual

[zygot]

Diverting VCC1V8 from VCCAUX isn't a great idea, especially for a board that has less than a robust design.

A much better option is one that you don't mention. Put a logic level converter between your external device and the CMOD IO pins so that the FPGA sees logic compatible with one of the available 3.3V IOSTANDARD options.

[DanielD]

What is the drawback of using the VCC1V8 for an IO bank? It is not directly related to VCCAUX except that it might cause some crosstalk, isn't it?

 

For sure I can use level translators. The reason why I don't want to use them as a primary approach is that the A7 board is used for a quick customer demonstrator setup. Therefore I want to keep the BOM count/complexity and mounting/manual prototyping effort as low as possible!

[zygot]

Before you can modify an existing board design you have to understand it. That means understanding how the power supply works and the Artix 35T power sequencing and dynamic voltage rail requirements. If you done that and simulated your new version, with all of the external components, then I suppose that you might be able tomodify the board design. Have you done that? ( I assume that the answer is no or you wouldn't be posting the question )

I don't know anything about your project or your customer's deliverables requirements. As a customer, I'd see a hacked-up demonstration board as a problem, or at least something that would prompt a lot of questions and additional design documentation. If I were your customer I'd probably not want to see a CMOD-A7 as a prototype platform without a lot of comprehensive design supporting material. I also wouldn't want to see an over-simplification of the project implementon requirements. I would want to see a proper engineering approach to the design solution. But that's me and what you do is between you and your customer.

Have you thought about a different FPGA platform that's more suitable to your project?

For what it' worth, it's been my experience that customers who have no idea what you are doing are the one that you don't want to work with. Edited April 4, 2023 by zygot

[DanielD]

Just for a reference:

After trial and error with different level shifter models, I used the following ones:

• SN74AVC1T45DBVR: For the clock.
• SN74AVC8T245PWR: For the data lines.

Clock speed is 50MHz.

With these level shifters I got acceptable rise and fall times. With other level shifters I had problems with the rise and fall times, even if it was not obvious in first hand from the datasheets.

BR, Daniel.

[D@n]

Glad to hear you got it working!