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Nexys 4 Test Speed DDR Memory With MIG and Vivado


alonsocd2006

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Figuring out the maximum data rate for read and write commands is straightforward, if using the MIG controller. Multiply the number of DQ pins connecting the FPGA to the memory device(s) by the DDR Controller PHY clock rate, double that because you are transferring data on both clock edges and divide the result by 8. For the Nexys Video with a 400 MHz MIG PHY clock and 16 DQ pins this works out to be 400*16*2/8 = 1600 MiB/s.

Is this a data rate that someone using the Nexys Video board should expect to see under all use cases, all the time? No. You don't write directly to DDR memory, but issue read and write commands to the controller in the memory. Also, DDR memory needs to be refreshed periodically, so there are periods when you can't issue read or write commands. For MIG DDR3 designs with read/write bursts of 8, it's possible to get an average of around 90% of the maximum theoretical data rate for large blocks of data. I've posted a tutorial here if you are interested:  https://forum.digilent.com/topic/22197-a-guide-to-using-ddr-in-the-all-hdl-design-flow/

Doing performance testing of external memory connected to FPGA devices is a lot more complicated than the simple explanation above. If you implement your design completely in HDL, then you can expect optimal results. If you are using a soft-processor to run your MIG controller to do random read/write operations then you can expect lower results. Usually, the maximum data rate that can be sent between an FPGA and DDR device doesn't have to be near the peak rate; and you can achieve timing closure easier in a complex design. This tutorial: https://forum.digilent.com/topic/25315-using-ddr-as-a-video-frame-buffer/ doesn't try issuing read or write commands to the DDR as fast as the MIG controller allows. It's still good enough for low resolution HDMI video work though. My point is that instantiating a MIG controller doesn't do anything. You have to design some logic to control the controller, and this is where reading from or writing to external memory can suffer in performance.

For other FPGA devices, some have hard memory controllers ( like the Spartan 6 and Cyclone V ). Memory controllers implemented in FPGA logic vary from vendor to vendor and often can be tweaked at the expense of resources and timing closure.

 

Edited by zygot
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