Mixed edge and level sensitivity list in Verilog

[Paul McKneely]

I am trying to model the 74x175 (a relatively simple discrete logic device) in Verilog and it seems to be coming up lacking. It is a quad flip-flop that clears the registers when the Clr input is low. But when Clr is high, it accepts the data into the register on a positive-going edge of the clock input. If I include (posedge Clk or Clr) in an always block, it clocks in the data values when Clr goes inactive even when Clk doesn't change. The load should only happen on the positive edge of Clk. If I take Clr out of the sensitivity list, then the registers will not clear. Does anyone have a solution to this seeming flaw in Verilog?

Edited March 20, 2023 by Paul McKneely
improve readability

[artvvb]

Hi Paul, welcome to the forum,

Sounds like clr is a reset signal and the 74x175 is a straightforward DFF. You'd need to be using an if statement to determine the state of the reset signal and choose to clear the register or load it from the input, doing this as logic inside the always block rather than in the sensitivity list. There are a bunch of examples for different types of resets in the link below, both synchronous and asynchronous. Note that Xilinx recommends using synchronous resets if you're actually implementing your design and putting it into an FPGA.

https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html

Thanks,

Arthur

[Paul McKneely]

On 3/9/2023 at 3:23 PM, artvvb said:

Hi Paul, welcome to the forum,

Sounds like clr is a reset signal and the 74x175 is a straightforward DFF. You'd need to be using an if statement to determine the state of the reset signal and choose to clear the register or load it from the input, doing this as logic inside the always block rather than in the sensitivity list. There are a bunch of examples for different types of resets in the link below, both synchronous and asynchronous. Note that Xilinx recommends using synchronous resets if you're actually implementing your design and putting it into an FPGA.

https://www.fpga4student.com/2017/02/verilog-code-for-d-flip-flop.html

Thanks,

Arthur

In an if statement you can test the level of a signal. Does Verilog have a way to test for a signal edge? Something like:

  if (↑Clk) DoSomething;

 

[Paul McKneely]

artvvb:

The example titled "Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level" seems to be exactly what the 74x175 does. I can now go off and continue simulation.

Thanks a bunch.

 

[Paul McKneely]

I guess the logic goes for Example #4 (which corresponds to the 74x175) is: If either transition in the sensitivity list happens and the Clr input is low, then it must reset regardless of which edge happened. I can see that. But if Clr is high when the always block is in effect, then the only way that the always block could be in effect is if there was a posedge on the Clk input since the Clr signal can't be high following a low-going Clr edge.

And to be clear, by "Asynchronous" you mean "level-activated" and by "Synchronous" you mean edge-activated. Is that Right?

 

Edited March 20, 2023 by Paul McKneely

[artvvb]

Hi Paul,

Not exactly level- and edge-activated. More that synchronous means "only affects things when the clock transitions" while asynchronous means "can affect stuff whenever", with the caveat that asynchronous signals usually need to be synchronized before use (at least in an FPGA). The clock is treated differently from data lines inside an FPGA, and whether a signal is considered synchronous with a particular clock matters for whether the tools can guarantee that that signal will be used correctly.

Thanks,

Arthur