I am trying to model the 74x175 (a relatively simple discrete logic device) in Verilog and it seems to be coming up lacking. It is a quad flip-flop that clears the registers when the Clr input is low. But when Clr is high, it accepts the data into the register on a positive-going edge of the clock input. If I include (posedge Clk or Clr) in an always block, it clocks in the data values when Clr goes inactive even when Clk doesn't change. The load should only happen on the positive edge of Clk. If I take Clr out of the sensitivity list, then the registers will not clear. Does anyone have a solution to this seeming flaw in Verilog?
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Paul McKneely
I am trying to model the 74x175 (a relatively simple discrete logic device) in Verilog and it seems to be coming up lacking. It is a quad flip-flop that clears the registers when the Clr input is low. But when Clr is high, it accepts the data into the register on a positive-going edge of the clock input. If I include (posedge Clk or Clr) in an always block, it clocks in the data values when Clr goes inactive even when Clk doesn't change. The load should only happen on the positive edge of Clk. If I take Clr out of the sensitivity list, then the registers will not clear. Does anyone have a solution to this seeming flaw in Verilog?
Edited by Paul McKneelyimprove readability
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