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DT9844 Finite Series of Ctr One Shot Repeat


Grata

Question

When controlling a DT9844 from LABView, is there a way to configure the counters to produce a finite series of pulses each time a gate is measured?

 

For example, if CTR0 is set as a gate based on a rising edge, if it sees a rising edge, can CTR1 be configured to produce say 5 pulses, each pulse being 50% duty cycle square wave with a 10ms period then stopping until the next rising edge is seen on CTR0?

If CTR0 sees a 1Hz square wave, each time CTR0 goes hi, CTR1 would generate a 50ms output of a 100Hz, 50% duty cycle square wave followed by lo for 950ms.

 

To cross reference, some NI products support Implicit Timing and Pause Triggers on Counters. See:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019M9CSAU&OpenDocument=&l=en-US

and

https://www.ni.com/docs/en-US/bundle/ni-daqmx/page/mxcncpts/gensnglefinconttrains.html

Edited by Grata
Found some cross referes to finite pulse train generation
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Hello @Grata.

A repetitive one-shot approach with the DT9844 does not work for your request.  Instead, consider using Rate Generation mode.

If your signal source is a 1 Hz square wave with a 5% duty cycle, then you could feed that signal to the 'Couter 0 Gate' pin and configure 'Counter 0 Out' for a 100 Hz square wave with a 50% duty cycle.  Reference the DtCtrRate.vi example from Data Translation's LV-Link.

image.png

 

However, if you cannot adjust the duty cycle of your 1 Hz signal, then feed your 1 Hz signal to the 'Couter 0 Gate' pin.  Next, configure 'Counter 0 Out' for a 1 Hz square wave with a 5% duty cycle and feed it to the 'Couter 1 Gate' pin.  Lastly, configure 'Counter 1 Out' for a 100 Hz square wave with a 50% duty cycle. 

In the block diagram below, I do not feed a 1 Hz signal to the 'Couter 0 Gate' pin, so the Gate Type is set to None.  I did however configure 'Counter 0 Out' for a 1 Hz square wave with a 5% duty cycle and fed it to the 'Couter 1 Gate' pin.  The last step was to configure 'Counter 1 Out' for a 100 Hz square wave with a 50% duty cycle.

image.png

 

Regards,

Fausto

image.png

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Fausto, thank you for the example.

In your example where the 1Hz 50% duty cycle signal cannot be adjusted, can the counters be configured to generate the 1Hz 5% signal for the Counter 1 gate when the 1Hz 50% goes high and when it goes lo?  This would allow the 5 100Hz pulses to be generated each time the 1Hz 50% duty cycle transitions.

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When configuring as described, there seems to be a non trivial delay between the rising edge of the 1Hz signal on the "Counter 1 Gate" pin and the "Counter 1 Out" pin.  Is it that the output signal on "Counter 1 Out" starts low, then goes high?  If so, is there a way to reverse this so that "Counter 1 Out" starts high, then goes low?

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Changing to low level makes the pulses occur when the 1Hz signal is low.

With gating set to high, and the Counter 1 100Hz 5% duty cycles, when the 1Hz signal goes high, the Counter 1 output goes high, 9.5ms later for 5 ms.  How can it be configured so that it goes high with the 1Hz signal for 5ms and goes low for 9.5ms?

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