Activate digital pins on Arty Z7 with Vivado

[roberto sanchez]

Hello, i am doing a program in Vivado to see serial data transfer in a 7 segments display. As the Arty Z7 doesnt have a 7 segment display in the board, i am doing it external in a protobaord... So i want to know if i can activate the 3.3v digital pins only with the constraint file, or i need to activate them with other software or i need to do more things?

...

i mean by only doing it with the constraint file by using these comands

## ChipKit Outer Digital Header

set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { anode[0] }]; #IO_L5P_T0_34 Sch=CK_IO0

set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { anode[1] }]; #IO_L2N_T0_34 Sch=CK_IO1

set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { anode[2] }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2

set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { anode[3] }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3

set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { anode[4] }]; #IO_L10P_T1_34 Sch=CK_IO4

set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { anode[5] }]; #IO_L5N_T0_34 Sch=CK_IO5

set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { anode[6] }]; #IO_L19P_T3_34 Sch=CK_IO6

set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { anode[7] }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7

 

Thank you, Roberto

 

[artvvb]

Hi Roberto,

The chipkit header pins are connected directly to the Zynq PL, so yes, as long as you have a design that has an anode output bus in the top module's port map (maybe, if an IPI design, driven by an AXI GPIO with GPIO ports made external) and these constraints, that will be sufficient to control the pins.

Thanks,

Arthur

[roberto sanchez]

On 2/6/2023 at 12:34 PM, artvvb said:

On 2/6/2023 at 12:34 PM, artvvb said:

Hi Roberto,

The chipkit header pins are connected directly to the Zynq PL, so yes, as long as you have a design that has an anode output bus in the top module's port map (maybe, if an IPI design, driven by an AXI GPIO with GPIO ports made external) and these constraints, that will be sufficient to control the pins.

Thanks,

Arthur

Yes, it worked. I set a bus signal as output in my block diagram and with the consraint file i controlled them. Thank you so much.