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Wav decoder: Pmod I2S2 outputs noise


BenBlaise
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I am currently working on a system that utilizes a Zybo Z7-10 board, an SD card, and a Pmod I2S2 to output a stereo wav file. The wav file stored on the SD card is in stereo format, with 16-bits per channel and a 44.1KHz sampling frequency.

The system includes a ZYNQ7, FIFO Stream, 2-stage Clock Wizard and I2S transmitter. The input to the first stage Clock wizard is 50MHz, obtained from the ZYNQ processor. A separate 50 MHz clock from the processor supplies the FIFO. The output of the first stage Clock wizard is configured to output 100 MHz, which serves as input to the second stage, which is further configured to output 11.2896 MHz. This output frequency is used as the MCLK and is in line with the specifications in the CS4344 data sheet.

I have designed the dividers for LRCLK and SCLK in VHDL using the MCLK. When measured, the LRCLK frequency is 44.2KHz, SCLK is 1.42MHz, and that of MCLK is 11.3MHz. These values could be due to the resolution of the oscilloscope used (small handheld one).

Upon examining the interaction between all the signals sent to the DAC using ILA, they seem to be in order and aligned with the CS4344 datasheet. LRCLK toggles at the falling edge of SCLK, and data at SD is clocked at the rising edge of SCLK. I have attached the ILA wave form window for reference.

However, the issue is that the sound output from the DAC is a continuous noise. I have also attached the sound for reference.

Please note that I only sent the data chunk to the DAC, excluding the 4 bytes "data" Subchunk2ID and 4 bytes Subchunk2Size. I sent both left and right channels, making 32 bits.

I also converted each 16-bit read per channel from little endian to big endian. For example, for the left channel, the following 2 bytes (34 FF) were converted to big endian (FF 34).

In the wave form below, tdata3 is the 32-bit output from the FIFO (L&R channels) that are clocked in by SCLK. Notice that when LRCLK changes (Low to high, as I am using the Left aligned spec), the first rising edge of SCLK clocks in Bit 31. I used a counter (counter3) to select the bit to output.

I would greatly appreciate any suggestions or solutions to this issue. Also, I would be happy to provide any additional information or design files to aid in troubleshooting.

  

 

image.thumb.png.1fc98c4fdd5431dd8927f637841af565.png

 

 

Edited by BenBlaise
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Hi @BenBlaise

I haven't reproduced the issue, but here are a couple things to check:

  • Make sure the mode select jumper is in the correct position.
  • Make sure the axi4-stream fifo is keeping up with the I2S controller, though based on throughput estimates in the AXI-stream fifo datasheet, I find it difficult to imagine that it wouldn't be able to keep up.
  • The CS4344 datasheet is a little confusing, because it covers all three of the 4344, 4345, and 4348 parts, which have slightly different I2S data formats. Check whether the spec you are building to actually applies to the 4344. Figure 8 "Left Justified" on page 13 of the datasheet looks to refer only to the 4345. If this is the issue, you might just need to shift each sample in each channel right one bit.

Thanks,

Arthur

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