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How to connect Microblaze IP and SpO2 Sensor: MAX30102 from Maxim Integrated?


Saikot Das Joy
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I have the Nexys A7-100T FPGA board . I wanted to measure the oxygen saturation level using SpO2 Sensor: MAX30102 from Maxim Integrated and microblaze processor. In Vivado Design suite , I connected AXI IIC IP with Microblaze IP .

Please help me how can I connect this sensor with the board, and what modification should I do on IP block Design? In the block design , other IP blocks are connected. I checked removing the AXI IIC IP block, Bitstream generation successes, But when I add AXI IIC IP, Bitstream generation fails. 

in bitstream generation, this shows an error . The error messege is:

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning}[get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SpO2_Sensor_scl_io, and SpO2_Sensor_sda_io. and [DRC UCIO-1]

Unconstrained Logical Port: 2 out of 22 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: SpO2_Sensor_scl_io, and SpO2_Sensor_sda_io.

block design.pdf

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Hi @Saikot Das Joy

These errors mean you need to add constraints to your design which will tell the tools which physical FPGA pins to connect the pins of the IIC interface to. The board files don't handle the AXI IIC for you. If you already have location constraints for those pins, make sure that the names match the HDL wrapper. I'd recommend taking a look through this guide, paying particular attention to the part where two AXI GPIOs are added, one with manually-assigned location constraints: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

Thanks,

Arthur

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