We purchased a Zmod DAC1411 board and tested it with Eclypse Z7 board with baremetal demo project.
The maximum sample update rate we can have is ~33Msample/second. This rate is lower than claimed 100Msample/second.
The only parameter related to update frequency is "frequencyDivider" in ZmodDAC1411 library. The update rate stops change when this parameter is set to <2.
It seems the HW IP used PS core clock (66MHz) for DAC output sample clock. Is this update rate limit caused by the provided hardware wrapper, "design_1_wrapper_hw_platform_0"? Can we change it to use higher DAC clock?
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LHji
We purchased a Zmod DAC1411 board and tested it with Eclypse Z7 board with baremetal demo project.
The maximum sample update rate we can have is ~33Msample/second. This rate is lower than claimed 100Msample/second.
The only parameter related to update frequency is "frequencyDivider" in ZmodDAC1411 library. The update rate stops change when this parameter is set to <2.
It seems the HW IP used PS core clock (66MHz) for DAC output sample clock. Is this update rate limit caused by the provided hardware wrapper, "design_1_wrapper_hw_platform_0"? Can we change it to use higher DAC clock?
Thanks,
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