Reading out AD1

[Udayan Mallik]

@artvvb I am receiving the following warning when I change the logic handling Port JB in the Eclypse Z7 from PmodACL2 to PmodAD1. Can someone explain to me what the warnings are referring to? The Create VHDL wrapper command produces these warnings.

Wrote  : </home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.srcs/sources_1/bd/lc402_Analog/lc402_Analog.bd>
Wrote  : </home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.srcs/sources_1/bd/lc402_Analog/ui/bd_22473550.ui>
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_bid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_rid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon/M00_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon/M00_AXI_wid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon/M00_AXI_arid'(1) - Only lower order bits will be connected.
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/synth/lc402_Analog.vhd
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_bid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/axi_mem_intercon/m00_couplers/auto_pc/m_axi_rid'(1) to pin: '/axi_mem_intercon/m00_couplers/M_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_AWID'(6) to pin: '/axi_mem_intercon/M00_AXI_awid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_WID'(6) to pin: '/axi_mem_intercon/M00_AXI_wid'(1) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/processing_system7_0/S_AXI_HP0_ARID'(6) to pin: '/axi_mem_intercon/M00_AXI_arid'(1) - Only lower order bits will be connected.
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/sim/lc402_Analog.vhd
VHDL Output written to : /home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/hdl/lc402_Analog_wrapper.vhd

Edited November 9, 2022 by Udayan Mallik

[artvvb]

Hey Udayan,

I wouldn't worry too much about these warnings. They're all related to "port width mismatches" which means that some individual port within an AXI interface has a different width on one side of the interface than the matching port on the other side of the interface. Typically if the downstream signal is narrower, the uppermost bits of the upstream signal get discarded. Similarly, if the downstream is wider, the extra bits at the top of the bus are pulled low. This *can* theoretically cause problems if the wrong signal gets truncated or zeros appended in, but it depends on what signal, and this kind of warning comes up in any number of example designs provided by various vendors.

That said, the warnings are referring to the axi_mem_intercon interconnect connected to the Zynq HP0 port, which seems to not be pictured in the screenshot of the block diagram. Could you provide some more screenshots or a project archive? S_AXI_HP0 is on the left side of the Zynq block, which is offscreen.

Thanks,

Arthur

[Udayan Mallik]

@artvvb Here it is. Please also note that the PMOD_AD1_0 used to be a PMOD_ACL2_1 in the original design.

 

Edited November 9, 2022 by Udayan Mallik

[Udayan Mallik]

@artvvb Here are more images with bus widths shown in more detail.

[Udayan Mallik]

@artvvb The project archive was 228MB. Do you still want to look at it.

[artvvb]

I don't see anything that looks off about the block design. It should be good. The DMA is likely configured for a 32-bit interface, which might be causing some conflicts when interface widths are propagated to the interconnect, since the Zynq's HP slave port is 64 bits. That said, I've seen designs that look pretty much just like this work before (that width mismatch shows up in many demos), so I wouldn't worry about it. I'd try using the bitstream in hardware to see if any errors crop up during runtime, and investigating whether these, or other, warnings might be the cause after an issue occurs. Vivado projects that use any IP have a tendency to spit out a lot of ignorable warnings.

The project archive shouldn't be necessary.

Thanks,

Arthur

Edited November 9, 2022 by artvvb