I am making a project for a Arty Z7-20 board, using Vivado/Vitis 2022.1. Everything works, except the DRAM.
The Hello World example crashes, the debugger gives memory access errors. It works when the linker script is changed so everything is located in on-chip RAM instead of DRAM.
When I do exactly the same in Vivado/SDK 2019.1 the DRAM works properly. Now I open that Vivado 2019.1 project in Vivado 2022.1, in read only mode, without rebuild/IP upgrade. Then I export bitfile etc and create a Vitis Platform project and a Hello World application project. DDR does not work.
The same happens when I download the Arty Z7-20 OutOfBox demo. It works when built with Vivado/SDK 2019.1, but not with Vivado/Vitis 2022.1
I have made similar Vitis projects for Arty S7-50(MicroBlaze), Eclypse Z7-20, and Avnet PicoZed 7030. None of these gave DDR problems.
What I find strange is that this problem seems to appear only for Arty Z7-20 and Vitis.
What is going on here?
How do I solve this/ Any workarounds?
Question
K. Ljøkelsøy
Hi!
I am making a project for a Arty Z7-20 board, using Vivado/Vitis 2022.1. Everything works, except the DRAM.
The Hello World example crashes, the debugger gives memory access errors. It works when the linker script is changed so everything is located in on-chip RAM instead of DRAM.
When I do exactly the same in Vivado/SDK 2019.1 the DRAM works properly. Now I open that Vivado 2019.1 project in Vivado 2022.1, in read only mode, without rebuild/IP upgrade. Then I export bitfile etc and create a Vitis Platform project and a Hello World application project. DDR does not work.
The same happens when I download the Arty Z7-20 OutOfBox demo. It works when built with Vivado/SDK 2019.1, but not with Vivado/Vitis 2022.1
I have made similar Vitis projects for Arty S7-50(MicroBlaze), Eclypse Z7-20, and Avnet PicoZed 7030. None of these gave DDR problems.
What I find strange is that this problem seems to appear only for Arty Z7-20 and Vitis.
What is going on here?
How do I solve this/ Any workarounds?
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