arty a7 100t DDR3 access is too slow

[varlub]

Hi,

I have implemented Cortex-M3 subsystem with DDR3 peripheral (Xilinx MIG controller) with core clock of 40MHz and DDR3 UI clock of 83.33 MHz with Phy Clock 333MHz.

ARM Cortex-M3 AHB Bus is connected to AHB 2 AXI Bridge (Xilinx) and then used AXI interconnect to connect the Birdge to MIG DDR3 module.
What I noticed is that once the arm core requests to read data from DDR3, it takes around 700 ns (which is 28 clocks @ 40MHz).

I believe this is too slow to access the DDR from arm core.

If any one see any issue with the above accessing the DDR or is there a better way to connect the Cortex-M3 to DDR such that the access time is far less?

Appreciate for your time.

-Varlu

 

[zygot]

8 hours ago, varlub said:

What I noticed is that once the arm core requests to read data from DDR3, it takes around 700 ns (which is 28 clocks @ 40MHz).

Hmm, 28 clocks sounds about right. The Mig core with DDR memory is really slow for random read operations. It's pretty good for reading large block of sequential memory. This is why modern processors fetch instructions and data out of onboard cache instead of external (DDR) memory.

Even if you design a core that attempts to random read and write operations with minimal latency the controller in the DDR has it's own latency which will discourage that kind of use..

[nsnreddym]

hi zygot,

   If i send sequential memory of 1000bytes what is the time it will take for above spec.

[zygot]

2 hours ago, nsnreddym said:

If i send sequential memory of 1000bytes what is the time it will take for above spec.

There's no way to answer such a question. You can figure it out for yourself by implementing a design and running it on hardware. I have a tutorial that might help: https://forum.digilent.com/topic/22197-a-guide-to-using-ddr-in-the-all-hdl-design-flow/

 

Understand that even if you have very good performance measuring logic in your DDR design you should not get the exact same answer every time you run a performance test. All you can do is transfer a large block of sequential memory and see what the average data rate between your design and the external memory is. If you have a series of mixed read or write requests for short blocks of data you can expect a large variation in performance. The first thing that you need to do is understand how DDR memory works. For the most part DDR memory is not designed to be used directly by a processor or design. Modern processors have onboard cache that holds a snapshot of partial contents of the DDR memory, and that's where short data read and write operations should be done. Of course it's possible to use DDR differently for specific applications.

Edited March 31, 2023 by zygot

[nsnreddym]

Thank you Zygot, I will go through the post and get back to you