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Basys 3 7 segment display on while not used in configuration


Anthocyanina

Question

Hi! so, today my Basys3 board arrived, and i uploaded the blink bitstream generated from following the tutorial, and I notice the 7 segment display is lighting up dimly. The display is not used in the blink verilog code, so I am wondering why it is lighting up. If i don't upload the bitstream, everything is completely off, and when running the default configuration it comes with out of the box, the segments properly light up as they count up. Any idea what might be happening? 

Thank you!

blink.png

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Hi @Anthocyanina,

From the FPGA's perspective, the seven segment anodes and cathodes are active low. By default, when the FPGA is configured, Vivado applies a weak pulldown to each of the unused I/O pins - pulling the outputs to ground while allowing an external pullup resistor to override it if necessary. It might have been possible when designing the board to avoid the 7seg illuminating in this situation by including pullup resistors on the nets connecting the FPGA pins to the display, but these were not included.

Before programming the bitstream into the board, the IO pins are left floating - no pull up or down - so there's no path to push current through the display.

The default after configuration can be changed, either by including ports for the anodes or cathodes and pulling them high, or by setting the default pull for unused pins to either pullup or pullnone (which could make other stuff happen, like illuminating unused LEDs, since doing so affects everything). See here for more info: https://support.xilinx.com/s/question/0D52E00006hpZVASA2/what-is-the-pin-state-if-i-didnt-use-them?language=en_US

Thanks,

Arthur

 

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Thank you @artvvb! being completely new to FPGA it took me a while to figure out how to do it, so I'll leave it here in case anyone else ever wonders about this while following the tutorial for the first time.

module blink(
    input clk,
    output led,
    output reg [3:0] an //added the anodes as outputs
 
 );
reg [24:0] count = 0;
 
assign led = count[24];
assign an =4'b1111; //assigned the anode outputs as high

always @ (posedge(clk)) count <= count + 1;

endmodule

 

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