Ethernet Port in Eclypse Z7

[Udayan Mallik]

@artvvb I am working on enabling the Ethernet port in Eclypse Z7.

In the block diagram I see that ENET 0 is checked. When I double click ENET 0 I am taken to a page where I select MDIO (MIO 52 ... 53). However, no PINS are created as result. Without pins I cannot create a constraints file. In addition - after making the selections and closing the dialog box, I reopen the dialog box to check whether the selections are still in place. They are NOT. Is this an error? How do I enable the Ethernet link in Eclypse Z7.

 

 

Edited September 22, 2022 by Udayan Mallik

[Udayan Mallik]

@artvvb

After much experimentation my lwip_echo_server routine is now operational. I can ping an Eclypse Z7 card. Since I use Vitis 2021.2 a large part of online help tends to be useless. I proceeded as follows.

 

1. To confirm that the Realtek PHY chipset can communicate with a Zynq FPGA I used the document found here https://media.digikey.com/pdf/Data Sheets/Digilent PDFs/Eclypse_Z7_HRM_Web.pdf 

2. To use lwip resources I altered the Board Support Package in Vitis.

 A. In the Platform project - Double click the Platform.spr file.

B. Click the ps7_cortex_a9->Zynq fsbl->Board Support Package Tab in the drop down menu.

C. Click on the "Modify BSP Settings ..." tab near the top of the page.

i. In the Overview tab - Select lwip211 libraries.

ii. Then click the Standalone tab.

Set the use_axieth_on_zynq to 0 (since the ZYNQ GEM will be used).

D. Click the ps7_cortex_a9->Standalone on ps7_cortex_a9_0

E. Click on the "Modify BSP Settings ..." tab near the top of the page.

i. In the Overview tab - Select lwip211 libraries.

ii. Then click the Standalone tab.

Set the use_axieth_on_zynq to 0 (since the ZYNQ GEM will be used).

 F. Create a new Application program with the lwip_server_echo option (instead of Hello World) and voila! You have ethernet connection. You can ping IP address 192.168.1.10.

Edited September 23, 2022 by Udayan Mallik

[artvvb]

MIO peripherals - the various hard cores in PS - don't require constraints unless you are routing them through the PL via EMIO. These are dedicated multiplexed input/output lines that get routed to specific pins depending on the configuration of the Zynq Processing System. That is to say, the ethernet already gets enabled when you apply the Zynq preset from the board files. This is effectively the same as how you would enable a UART connection through the USBUART bridge, the UART0 and UART1 controllers are also PS peripherals that route through MIO.

Thanks,

Arthur

[Udayan Mallik]

@artvvb I have used the emacps download (From the Board Support Page) to get things going -- I however see runtime errors. I see the three following errors in Run Time: Length Mismatch, Data Mismatch, Error setup PHY loopback.

1. My PHY Layer is implemented with a Realtech RTL8211E-VL chipset. I found that the emacps routines cannot operate that specific PHY layer. I looked at someone's implementation on Youtube that claims to have solved the problem. and she merely deleted the "exit on error" lines of code from her software. I see that when I do the same, I see some form of output on the receiver PC (Wireshark). I am not sure whether what I am looking at is correct.

2. How do I find the IP address of the device.

3. I am also working with LWIP. Will it be able to establish an Ethernet connection given that it also has to communicate using the RealTech PHY?

Edited September 20, 2022 by Udayan Mallik

[Udayan Mallik]

The Eclypse Z7 card is designed to use the lwIP routines to communicate on the Ethernet bus. https://media.digikey.com/pdf/Data Sheets/Digilent PDFs/Eclypse_Z7_HRM_Web.pdf "For getting started using the ethernet port in a bare-metal application, Xilinx provides a lwip TCP/IP stack that can be automatically generated in Xilinx SDK along with an echo server example."

[Riccardo]

Hello Udayan,

I tried to follow your tutorial on how to setup the ethernet port, but I am not able to ping that address with my laptop. Currently I am using an USB-ethernet adapter because my laptop do not have an ethernet port, but I'm quite sure that it is not representing a problem since I used even in other projects.

Is the procedure valid for every PL that uses the Zynq block? I am using Vitis 2021.1 an this is the serial monitor:

from this I understand that the ethernet link is settled, but it is not working. Do this happened to you while trying?

Thank you in advance

Riccardo