PMOD IOX add-on access via I2C

[Ana]

Hello

I am new to the forum as well as to Digilent boards. I currently have a genesys2 dev kit. I am talking to it over ethernet and using the 4 PMOD GPIOs that come with it. I have to read in more inputs( outputs in future) and hence was wondering what is the best way to approach it. I came across the PMOD IOX add on. 1st question- would that work with my board? second, it looks like this addon board can talk to the digilent board via i2c. To use this add-on, on the vivado side, do I need to drop an AXI_iic IP  and go from there? Are there any sample/demo codes that I can use to get started? 

Thanks!

 

 

 

Edited September 9, 2022 by Ana

[JColvin]

Hi @Ana,

I don't know why there are screenshots in your post about a Zynq based design in your post, but the Pmod IOXP can certainly work for this board in the way that you are hoping (though I don't believe that Digilent has any existing FPGA designs to communicate with the embedded ADP5589 over I2C).

Thanks,
JColvin

[Ana]

Thanks for your reply. I don't know why the Zynq based design showed up in my question. Sorry about that. 

Few questions-

1. The addon board has a pin configuration for SCLK, SDA, VCC and GND. These don't match with my connectors. Do I make a cable in between to accommodate that?
2. The 12 pin PMOD connectors on my board go to various pins on the FPGA. They do not go to SCLK or SDA on the board. Can I just designate the pins as SDA/SCLK? 
3. Currently I use the PMOD connectors just as GPIOs. I connected the various I/O signals in my block diagram to pins on JA, JB, JC, JD. That is not going to work now if I were to connect this I/O expander. I didn't invoke a PMOD IP to realize my design. Do I have to do so now? 
4. I know I will need to write the i2c protocol/communication part in .VHD, but I am not sure how to access the various I/Os after that. 

Thanks

Ana

 

[JColvin]

Hi @Ana,

1. No; you can specify which pins the SCLK/SDA in your module are associated which FPGA pins via the xdc file. GND and VCC are "hardwired" to their locations on the Pmod host port.
2. Yes; SCLK and SDA in terms of general application are just I/O pins that happen to be pulsing to logic high and logic low levels that follow the I2C protocol. Unlike a microcontroller with designated I2C pins, the Genesys 2 (and other Digilent FPGAs) can use any of it's Pmod pins with an additional PULLUP TRUE "flag" added to .xdc line of interest, akin to:

   set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { scl }];
   set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports { sda }];

3. You don't have to use a Pmod IP, no. The Pmod IPs just add a level of convenience in terms of associating the FPGA pins (via the .xdc) to whatever AXI module is being used to facilitate the communication. Though I suppose if you wanted to, you could just tell Vivado that you are using a Pmod HYGRO IP or something like that and then simply update the corresponding .c and .h files for that I2C Pmod to instead talk to the registers used by the Pmod IOXP.
4. If you are using just straight VHDL, you would control and communicate with the pins in the same way that you would for any of the buttons or switches. The Pmod pins just happen to not be connected to a permanent peripheral; the FPGA itself doesn't care so long as whatever is on the other side of the FPGA pin operates at the logic level that the bank is powered at (3.3 V CMOS in this case). Otherwise, if you are planning to use a processor like Microblaze, I would definitely recommend repurposing an already existing IP that I mentioned in 3.

Let me know if you have any questions.

Thanks,
JColvin

[Ana]

Hi 

Thanks for the detailed answers.

Pt 1 and 2 are well taken. Can I use an AXI IIC IP core to realize this setup? I was thinking in the lines of having an AXI_IIC IP connected to my microblaze. The IIC port on the IP is connected to SCL and SDA in the constraint file. I chose the board interface as custom. I am not sure if I am constraining it correctly. Output port is IIC, so should constraints be....get_ports{ IIC_scl_t} etc or what I have below should be fine as the correct pin assignment is what matters. 

set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports {IIC_0_SCL_IO}];#IO_L12P_T1_MRCC_14 Sch=ja_p[2]//SCL
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33 PULLUP TRUE} [get_ports {IIC_0_SDA_IO}];#IO_L12N_T1_MRCC_14 Sch=ja_n[2]//SDA

Now after generating bitstream, in Vitis, I can  specify the IIC address - AXI IIC ( from xparameters.h file) and io_expander address ( my expander io address). Once that is established I can send and receive data on the data line and based on the AXI IIC IP register space I can check the TX_FIFO and RX_FIFO for sent and received data. 

Will this method work or am I missing something?

 

Attached is my block diagram with AXI_iic

 

. 

[JColvin]

Hi @Ana,

I've been told that this approach is not as straightforward as you might hope (though in principle I would think this would work since I have done something similar with AXI Uartlite) and that it would be easier to instead use an existing Pmod IP like the Pmod HYGRO and instead change it's main.c to adjust the registers of the I2C device as needed.

Thanks,
JColvin