Use the PLL output 100MHz on CMOD A7

[yunwei]

how can I use the PLL to take the external clock output 100Mhz on cmod a7?

I tried to use IP of Clocking Wizard,
Set the input frequency 100Mhz and output frequency 100Mhz, then import to CMOD A7,
The result after taking the measurement is only 12Mhz.

I would like to know how to achieve PLL maximum output frequency in DS181.

[zygot]

If you set up a PLL to have a 1X input/output frequency ratio you should expect to see that, which is what you report. Try using 12 MHz as the input clock frequency.

It's true that the datasheet states that the maximum PLL_Fmaxout is 800 MHz for all Artix devices and all speed grades. That doesn't necessarily mean that you can generate such a frequency from a 12 MHz input frequency. There are other parameters that limit MMCM and PLL output frequencies such as PLL_Fvcomax. Let's say that you could generate an 800 MHz PLL output clock; what are you going to do with it? Fmax_bufg is 464 MHz for the -1 part. Seeing evidence of such a clock on an ouput pin that you could measure would be unlikely, even with very expensive FET probes and a high end scope. You might have some luck doing this by inference using a divided down version of the PLL clock.

The Vivado clocking Wixard is useful for limiting expectations to something realistic. Closing timing on a design that uses a very high speed global clock near the maximum might be challenging.

The maximum OSERDES toggle frequency for your device tops out at 950 Mbps in DDR mode implying a 475 MHz BUFIO clock which is within AC specifications but too high for any global clock buffer. Edited September 3, 2022 by zygot

[yunwei]

Thanks for your responce.

Because I have an experiment for verification and testing that requires 100MHz clock source from CMOD A7-35T to output 100MHz and 50MHz frequencies.

The datasheet of CMOD A7-35T shows that the internal clock is supported, but this module cannot be generated.
Do I need an external clock? But if i have to use external clock it means internal clock is not supported.

 

Edited September 7, 2022 by yunwei

[zygot]

You can easily create a 100 and 50 MHz clock sources from the 12 MHz external clock input on the CMOD A7 boards. Just specify 12 MHz as the input and whatever frequency you want as the output(s) of your PLL or MMCM instantiation using the Vivado Clocking Wizard. The CMOD-A7 has quite a few clock-capable pins available if you want to supply an external clock source, and you can use that external clock as an input to a PLL or MMCM.

I suggest that most users take advantage of the Clocking Wizard for creating global clocks of arbitrary frequency because it takes into consideration the quality of the output clock with regard to jitter. All derived clocks suffer from jitter when generated by FPGA PLL and MMCM hardware. You can specify a limit to this jitter in the Wizard. What this means in practical terms is that if you have, say a 10 MHz input clock connected to your PLL and want an 11.11105 MHz clock output the wizard will supply an output as close as possible to that specification within the limits of the jitter specification you supply... or possible let you know that it can't provide a clock to your specification. The wizard also has a drop down list of potential output clock frequencies that you might want to consider if that's convenient. If a clock output frequency can be defined as an integer multiple and integer divisor of an input frequency while meeting the maximum VCO specification for your device then none of this is a problem. Common clock frequencies for things like video and communications are generally very odd frequencies so this is where problems occur.

[yunwei]

Most modules of other A35T designs support internal clocks higher than 450MHz, as described in the Artix7 FPGA datasheet itself.
Is it a setup or programming consideration? Or are there other issues to deal with?

[yunwei]

Here is my setup using CLOCKING WIZARD in VIVADO, is there something I haven't set that is preventing my actual measured output from reaching 100 Mhz.

 

 

 

 

 

Edited September 8, 2022 by yunwei

[zygot]

I'm not sure why, when Ive mentioned that the tools are giving you exactly what you are requesting ( for the 3rd time now ) , you keep being disappointed with the results.

Showing a picture as proof that I've been unable to communicate this to you isn't going to change the results. When the Clocking Wizard asks for information about the Input Clock frequency, why are you telling it that it's 100 MHz when in fact it's 12 MHz? How do I know this? Because you've told me this and that's the only external clock that's available for your board.

Naming a signal clkin_100M doesn't make it a 100 MHz signal when the physical clock source frequency is 12 MHz.

I suspect that you are using the IPI flow and that this is a big cause for your confusion. The names on the IP entity port are not important. It's the name of the signal that you connect to the IP port when you instantiate the IP that is important.

For a simple design I really encourage people to use the HDL flow. If you want to use VIVado IP, and the Clocking Wizard is one that most people should be using instead of macro instantiation, then create a native form and keep the default signal names. When you generate the output products you will get a Verilog or VHDL entity file and an instantiation tmeplate that you can copy into your design source file. It's not point and click, but because you have full control over the soures you are forced to think about the details.. and most importantly the tools aren't doing something behind your back that's not what you want to do.

The IPI flow is not appropriate for students and beginers trying to learn programmable logic design.

The IPI flow is good for FPGA vendors trying to hoodwink potential customers into thinking that FPGA design isnt really as hard as it appears to be. It's good for FGPA vendors who want to push customers toward the most expensive device possible. The IPI flow is good for teachers who don't do FPGA development for a living and just want an easy way to get through a class with as little effort as possible. It's good for FPGA vendors who want to lock their customers into being dependent on one FPGA vendor. The IPI flow is good for FPGA board vendors who think, falsely, that it's a good way to avoid the cost of providing support for thier products.The IPI flow might... might be a resonable way for an expert in FPGA design and development to quickly prototype a design concept or idea as a way to estimate suitability for a particular device. The IPI flow hides things and almost always this is not good for the user in the long run. Edited September 8, 2022 by zygot