HW Platform with AXI PS2 IP; Driver not compiling on Vitis 2022

[Gabriel Uribe Romero]

Hello,

I created the attached block design on Vivado 2022.1. The design includes an AXI PS/2 IP Core that is used to convert PS2 signals to the AXI interface used by MicroBlaze processor. I am using a Basys-3 although I know that the AXI PS/2 IP Core was generated for the Nexys video board.

After generating the bitstream file and importing the platform into Vitis, I am trying to compile a very simple piece of code (see below). Basically a Hello World type application.

#include "xil_printf.h"

int main(void)
{
    xil_printf("Entered function main\r\n");
    while (1)
    {

    }
}

However, I am getting a bunch of errors (as shown on the screenshot below). I believe the errors are associated to the Makefile of the AXI PS/2 IP Core that was generated by the tools.

There is a solution documented on the Xilinx Website: https://support.xilinx.com/s/article/75527?language=en_US

I tried to follow the solution and I couldn't make it work for me even after modifying the Makefiles.

Has anyone tried to use the AXI PS/2 with the MicroBlaze using the Basys-3 board and Vivado 2022.1 and Vitis 2022.1.0?

Any clue on how to solve the issue? Please advise.

Thanks,

CEH.pdf

[artvvb]

Hi @Gabriel Uribe Romero,

The Makefile for the AXI PS/2 IP's drivers was updated with the suggested fixes a while back, though it's possible that you downloaded a different version of it. What were the contents of the file before editing? The most-up-to-date version of this IP is the one at the head of the master branch: https://github.com/Digilent/vivado-library/archive/refs/heads/master.zip

Could you provide the contents of the build console for the hardware platform? Makefile errors can be pretty obscure, and the context around where they show up in the log makes it a lot easier to tell what went wrong. I've attached a screenshot showing how to get the build log.

In a vacuum, I'd recommend resetting the BSP sources (open platform.spr, open each Board Support Package and pick Reset BSP Sources) or recreating the workspace from scratch, including the hardware platform, since sometimes links can get broken between projects. Vitis's occasional use of absolute paths mean that trying to manually move a workspace around a filesystem (for example) can break links between projects, causing files to not get delivered to the compiler or linker properly.

Thanks,

Arthur

[Gabriel Uribe Romero]

Hello Arthur,

Thanks for providing an answer to my question.

I think you are right, it looks that I downloaded a previous version of the AXI PS2 v1.0 core. I obtained the AXI PS/2 v1.0 core as part of the IP available on the Zmod IP Version 1 Support for Vivado 2019.1, this Vivado library is available at the Digilent Github repository under the following URL: https://github.com/Digilent/vivado-library/releases/tag/zmod%2Fv1%2F2019.1-2. The library is tagged as 'latest' (refer to the image below), so, I probably got confused because of that.

Since I added this library to the IP Catalog of my Vivado v2022.1, the AXI PS/2 Core generates the driver using an old Makefile when exporting the Hardware platform from Vivado into Vitis.

Even though I was not using the most recent driver, I was still able to solve the my building issues by manually modifying the Makefile associated with the AXI PS/2 driver on my Hardware Platform inside Vitis. Such Makefile is typically found under "$HW_PLATFORM_ROOT_PATH/microblaze_0/standalone_microblaze_0/bsp/microblaze_0/libsrc/axi_ps2_v1_0/src/". Keep in mind that I am using a MicroBlaze soft processor and no operating system on my hardware platform. This is reflected in the path that I just shared and might be different for other developers using other processors, OS and board support package settings. Other users that want to take advantage of my solution would have to consider this.

Anyway, once I determined which Makefile was associated to the AXI PS/2 Core, I updated it as shown on the image below. The highlighted text are my manual updates and were based on the Xilinx Solution 75527 that I mentioned on my previous post and other answers that I found at the Xilinx Forums.

While I definitively think that the best way to solve this issue is by simply updating my catalog with the latest version that you provided, I wanted to share that there are some workarounds for those of you that for any reason do not have the latest version.

I have some additional questions about this core:

1.  When adding the AXI PS/2 IP Core into my Vivado Platform, I noticed that the core is tagged as (Pre-Production), what does this actually mean?

2. The AXI PS/2 1.0 IP Core User Guide mentions on section 3 Performance that "Sending data to a device is done by writing one byte at a time to the TX data register". Then, the Nexys-Video-AXI-PS2-Keyboard Demo Application (available at https://github.com/Digilent/Nexys-Video-AXI-PS2-Keyboard/blob/master/sdk/appsrc/demo.c) implements a function called KbLeds on line 582. This function calls the axi_ps2_SendByte function from the AXI PS/2 IP Core driver API. The axi_ps2_SenByte function is actually implement on file axi_ps2_l.c. The header comment of the axi_ps2_SenByte function at axi_ps2_l.c file mentions the function only operates under polling mode (Please refer to the image below). Now, I am trying to build an interrupt-based application and I am having runtime issues with my application every time I press the NumLock, ScrollLock and CapsLock keys. The LED do not respond all the time and I suspect that part of the problem is that this function only operates on polling mode.

My question is if you can actually generate an interrupt on the AXI PS/2 IP Core if you send information from your board to the Keyboard?