Fail to connect JTAG_HS3 to my XC7Z007 board

[George Lai]

Dear All, I had design one XC7Z007 board, it was subset of AVNet MiniZed, PMIC was replace with DC to DC, the Wireless, FTDI, Nand, Motion, Temperature, Audio were eliminate. Adept was success to program (see Adept.jpg), but the Vivado fail to connection(see VivadoErr.jpg), and I had turning JTAG freq to 125KHz, the "done" LED also no light, finally, I test SDK program FPGA, and the error still same(see SDKerr.jpg). I had check hardware, osc/voltage/LED, actually, all were no issue. the "done" LED had no light, but the Adept was show success, it seems a bug, do I need to upgrade my vivado to newest version(current use 2018.3). 

Edited August 29, 2022 by George Lai

[JColvin]

Hi @George Lai,

I am a little surprised to see this; normally it is the other way around where Adept cannot connect to any downstream FPGA/SoC while the Vivado Hardware Manager or SDK is open and can see a target. Normally if the board is not detected by Vivado that is indicative of cable drivers not being properly installed, but with the Digilent Adept system installed this would not be an issue (as the cable drivers that Xilinx uses originally come from Adept).

I do recall having an issue where if I had both the USB-UART and JTAG HS3 connected to a Zedboard that I would have to power off the board before I could switch connections between Adept and the Vivado Hardware Manager, but based on your picture that should not be an issue here.

Mostly this is to say that I am not sure what the issue might be (though I was hoping I would come up with an debugging option as I was typing this response).

Thanks,
JColvin

[Paul Chang]

Hi@JColvin

 From George's feedback: (He is my client)

Hardware AE's diagnostic: JTAG has no test PS-POR-B situation,

if you had check PS-POR-B, Vivado may not say ‘NO_device_found’.

Because system was locked by PS-POR-B.

Thanks for your help.

Paul

 

[JColvin]

I see. The JTAG HS3 supports PS-POR-B, but it expects a 1.5k Ohm or larger pull-up resistor on the line since that is what is normally used on Xilinx made boards (as noted in the JTAG HS3 Reference Manual here: https://digilent.com/reference/programmers/jtag-hs3/reference-manual#xilinx_zynq-7000_and_soc_support).

Thanks,
JColvin