SD Host Controller on Genesys 2 Board - IO delay constraints

[Unquestionneur]

Hai,

I wish to implement my own SD Host controller which support SD mode in Genesys 2. Could somebody advice me how to set the IO delay constraints for SD data and cmd lines? My controller supports 25 as well as 50 MHz 4 bit SD Mode.

Many thanks in advance.

 

[Unquestionneur]

Any help in this regard?

[zygot]

What exactly are you looking for?

The place to start is with Vivado user's manuals available for your version of VIvado. You need to start with the concepts of how the tools use timing constraints. You then need to know what the appropriate constraints are and the proper syntax ( which frequently changes with new tool versions ). There is a constraints wizard if you open the Synthesis. The tool isn't that intuitive but may be helpful. You might find published constraints for things like Ethernet PHY interfaces helpful... though beware of obsolete syntax. Vivado provides a template for all constraints, though the information might not be up to date. The TCL console is another way to get information ( again perhaps up to date, perhaps not ). I have had the experience of Vivado suggesting constraint syntax that it then rejects.

Basically, you have a reference clock used in your HDL and want to specify setup and hold timing relative to the active edge for both input and output signals. You will also need to know the timing specifications for an SD card that you want to use. Vivado has always made it somewhat difficult to figure out what the actual clock reference name is, especially for PLL and MCMM clock outputs. Quartus for Intel development isn't much better. I really don't understand why they don't do a better job of it.

Make usre that you read all of the Synthesis and Implementation messages to check that your constraints haven't been ignored due to syntax.

[elodg]

Buckle up!

 

SD_Card_Interface_Timing_v2.pdf

Edited September 14, 2022 by elodg