Using the Genesys-ZU UART1 with the bare metal driver
I'm using Vivado and Vitis 2020.1 projects created from the bare metal Genesys-ZU Hello World example as a base to create an application which will be controlled over UART1. In Vivado, I've enabled UART1 and mapped it to EMIO pins.
Using the Xilinx UART polled example UART0 passes and UART1 fails XUartPs_SelfTest().
Is there something special that needs to be done to UART1 to get it to at least pass the self-test?
I've also:
Created my own base project using XSCT and replac
Hi @John J,
I was able to get the UART1 PS selftest (and external loopback) working with EMIO. In my initial test I had forgotten to make the UART1 module on the UltraScale+ IP in the block design external (and then of course constrained them to a pair of external pins, in this case a pair of Pmod pins). With regards to the XUartPs_SelfTest, a return of zero is a successful test (i.e. no error codes thrown). I've provided the main.c that I used (which also has 4 buttons and LEDs enabled in the
