Behavior during Artix-7 35T sys_rst period

[hayato yonekura]

Arty-A7 35T rev.C with Artix-7 35T reference design shows abnormal clock output to DDR3 during MIG sys_rst period.
Reference design: https://github.com/Digilent/Arty/tree/master/Resources/Arty_MIG_DDR3?_ga=2.222865179.1627767032.1659918810-650189140. 1643348667

sys_rst=High, 430MHz is output (abnormal)
sys_rst=Low, 330MHz is output (normal)

No clock should be generated during sys_rst. Is there any possible cause?

[zygot]

The answer to your question is somewhere in the design sources. If it's important enough you can find the answer. Fortunately, since this has to do with clock generation and resets, you can narrow down the number of source files that you need to focus on. The exercise is well worth the effort, even if only for educational purposes.

I've not come across anyone even interested in logic behavior during reset as most people are singularly focused on what's happening when reset is not asserted. It's still a good question to pursue as logic resets aren't as straight-forward as most people would assume.

Can I assume that you came across this because the design isn't working as expected? Edited August 8, 2022 by zygot

[hayato yonekura]

Dear zygot.

Thank you for your response.

The reason for the investigation is that the power consumption was higher than expected when reset was enabled, so we followed the cause and found an unexpected clock output from DDR3_CK_P/N.