About PMOD USBUART question

[Paul Chang]

Dear Sir,

Because Arty's J10 was broken.So my client bounght  PMOD USBUART/Power Adapter /JTAG HS2.

1.About PMOD USBUART's Jumper JP1. (Does it use default settiing?  Set JP1 as SYS3V3 (remove power adapter )and it can provide the power to Arty but it can not download)

When host computer connect with PMOD USBUART .The device manager show recognize this device (COM 3,It is FTDI driver).

2. Power on power adapter and download below project bit file to Arty via JTAG HS2.

Arty's LED is work fine. But PuTTY does not has any output.  Do you have any suggestion?

 

Vivado Porject

 

xdc file (https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc)

## Pmod Header JA
#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { UART_0_rxd }]; #IO_L4P_T0_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { UART_0_txd }]; #IO_L4N_T0_15 Sch=ja[3]

SDK

putty setting:

 

Best Regards,

Paul

Edited July 13, 2022 by Paul Chang

[JColvin]

Hi @Paul Chang,

I am not certain what the default option is on the Pmod USBUART, but you would want the JP1 setting to be on the LCL side so that the attached system board (the Arty) is powered independently from the Pmod USBUART. You do not want to attempt to power the Arty board through the Pmod itself; it can only supply up to 50 mA total anyways which is simply not enough.

I cannot tell from the attached image, but I presume that the UART port on the AXIUartlite block was set to external and the Board Interface was set to "Custom" (which can be adjusted when you double click on the IP block to adjust it's configuration).

Otherwise, you will need to swap the rxd and txd pin assignments in the .xdc file so that it is the following:

set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { UART_0_txd }]; #IO_L4P_T0_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { UART_0_rxd }]; #IO_L4N_T0_15 Sch=ja[3]

This is because (as per the https://digilent.com/reference/pmod/pmodusbuart/reference-manual#pinout_description_table) the RxD pin on the Pmod is expecting to receive data from the host FPGA to the Pmod, so correspondingly the UART TxD pin needs to be assigned to that same pin 2.
I was able to verify that this configuration (Pmod USBUART also attached to a Pmod port with a JTAG module configuring the FPGA) on an externally powered Arty 35T.

Let me know if you have any questions.

Thanks,
JColvin

[Paul Chang]

Hi @JColvin,

I swapped the rxd and txd pin assignments in the .xdc file and it's work fine. 

I need to check the spec more detail.

Thanks for your help.

 

Best Regards,

Paul