Is it possible to use Verilog as a test bench for my VHDL design files?

[nmarks77]

I am using Questa and doing a basic VHDL frequency divider. I was wondering if theres anyway to do this. Also I was told by my boss we can not use signal_spy().

`include "tb_zb01.vh"
`timescale 1 ns / 1 ns

module tb_zb01;

   //***************************************************************************
   // test bench signals
   //*************************************************************************** 
   reg               clk100;
   reg               rst_sync_100;
   
   //***************************************************************************
   // clock generation, 100 MHz
   //***************************************************************************
   initial begin
clk100=0;
forever begin
          #5; clk100 = ~clk100;
      end
end
   //***************************************************************************
   // generate a reset in the all domains
   //***************************************************************************
   initial begin
rst_sync_100<=0;
repeat (10) @(posedge clk100);
@(posedge clk100) rst_sync_100 <= 1;
repeat (21) @(posedge clk100);
@(posedge clk100) rst_sync_100 <= 0;
end
   //***************************************************************************
   // this is the DUT
   //***************************************************************************
   zb01_top dut(
         // misc
         .i_clk100                   ( clk100 ),
        .i_rst_sync_100             (rst_sync_100)
         );
   
endmodule // tb_zb01

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 

library work;
use work.epack.all;

entity zb01_top is

generic(
      SUPER_SECRET_RUN_FAST : integer := 1
      );

port(
    -- Outputs
    o_led_drv_01     : out std_logic;
    -- Inputs
    i_clk100       : in  std_logic;
    i_rst_sync_100 : in  std_logic
    );

end entity;
 
architecture rtl of zb01_top is

signal counter: natural range 0 to 100000000 := 0;
signal alive         : std_logic := ZERO;

begin

process(i_clk100)
begin

if (i_clk100'event and i_clk100 = ONE) then
      if (i_rst_sync_100 = ONE) then
        counter    <= 0;
        alive      <= ZERO;
      else
        if (counter = (HALF_CYCLE - 1)) then
          alive   <= not alive;
          counter <= 0;
        else
          counter <= counter + 1;
        end if;
      end if;
    end if;
end process;

o_led_drv_01      <= alive;

end architecture;

 

[zygot]

I doubt that you'll find many Questa users reading you post, but I hope that you'll get lucky and prove me wrong .

I know that Intel has ditched ModelSim in favor of Questa but that's pretty recent. I'd say that the best place to get an answer to your question depends on who your Questa vendor is. If it's Intel then you'll have to hope that their documentation will be helpful. If it's not then you'll probably have to get the details of mixed language simulation support based on your company's tool license, from your vendor's documentation.

An alternate might be to write your design in Verilog. Based on your signal spy comment you must have some knowledge of the differences between VHDL and Verilog in terms of their simulation capabilities.

Edited July 8, 2022 by zygot