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Need help with setting the FFT IP correctly


abose4

Question

I am trying to accomplish a simple FFT exercise using the LogiCORE FFT IP v9.1. I generated a 10MHz singletone sinusoid using LogiCORE DDS compiler IP v6.0 and feed it to the FFT IP. After calculating the absolute value of the output from the FFT, I get multiple frequencies as the FFT output. What I am doing wrong. Following is the simulation output. You can see the FFT_out has multiple peaks.

image.thumb.png.beda2184c21f02fe5b96beff49172ed1.png

Following is the block diagram I am using for this exercise:

image.thumb.png.98ce1cb658aac6c4d066c4e032e37d74.png

Let me explain the block diagram in detail:

  • sys_diff_clock is 50MHz and clk_wiz_0 is producing a 100MHz clk_out1.
  • dds_compiler_0 is set up as follows to generate a 9.9990844726562500000 MHz sinusoid:image.png.3f5c86e08c9a643b7e119e1c1a97ced3.pngimage.png.8186255887af4b8835f1bf4ef4574f1e.pngimage.png.414048d848881066f9e7c294b980d872.pngimage.png.1a6417a1e8304ef09540088e42f86527.pngimage.png.06242898121469439940919d159782f0.png
  • xfft_0 is set up as follows:
    image.png.82e43482b12bb1354d9ff3574025de54.pngimage.png.43f5654667bab52292c20c4d2b692833.pngimage.png.b7737241aebff6e7465f1111db52c488.png
  • xlconcat_0 produces a 32bit output by concatenating 16bit output from dds_compiler_0 as real and 16bit zeros from xlconstant_0 as imaginary part.
  • m_axis_data_tdata from xfft_0 is sliced into [15:0] and [31:16] as imaginary and real parts, respectively, and squared using mult_gen and added together using c_addsub_0 to form the absolute values.
  • Both mult_gen_x and c_addsub_0 uses signed operations. Finally, the output is FFT_out which should show a single peak.
  • In the simulation, I am showing everything as signed magnitude radix.
  • I am using Vivado 2020.2.

My question is why I am not seeing a single peak. Any help will be appreciated.

 

Edited by abose4
Extra figure removed.
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Hi @abose4,

I have not personally worked with Xilinx's FFT IP; maybe another community member will have some insight into your question, but you might have better luck post in on the Xilinx forums where some of the Xilinx employees will be able to see and respond to your question about the FFT configuration.

Thanks,
JColvin

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Is your transform length an exact integer multiple of the 10 Mhz input signal period? If not, this is expected behavior as you are seeing the spectrum of the input signal truncated to the transform length. Google "fft windowing bin leakage".

 

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