Arty Z7 capacity to handle noise spikes

[jeremy_delossantos]

Hi,

General question regarding the Arty Z7-20 ability to handle large voltage spikes (less than 10v) on the GPIO lines for a few micro seconds. One of our applications generates a lot of noise and we were wondering how much damage we were doing to the device. 

 

Thanks,

 

Jeremy  

[zygot]

If you think that ths is an issue I advise that you mitigate it.

For ESD issues there are specialized devices to mitigate this. You might be surprised how much ESD a gear spun by a toothed elastic band can create.

Large inductive loads, like motor windings and some relay windings are alos a problem that can be mitigated using diodes. The GPIO on Digilent FPGA boards only provide current limiting resistors on the standard PMOD interfaces as a form of FPGA protections. You can look at the schematics from other FPGA board vendors to see seamples of ESD protection. When connecting your FPGA IO to highly reactive loads you have some design work to do.

Modern FPGA device have internal protection diodes but these are not meant to address abuse by user application design failings. Edited June 13, 2022 by zygot