Critical Timing error with "Getting Started with Vivado and Vitis for Baremetal Software Projects" tutorial

[Rochus]

Hi all,

I am an embedded software engineer trying to teach myself FPGA prototyping.

I have been following the following tutorial "Getting Started with Vivado and Vitis for Baremetal Software Projects"

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

I am using the Nexys A7-100T board. I have followed the tutorial and validated the project, however when I go to implement the project I get critical timing errors. Below a few of the critical errors I get, and I have attached a screenshot of timing tab page.

 

[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports,  port btn_tri_io[0] can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74]


[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports,  port btn_tri_io[0] can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["/home/user/codeDepot/digilentTutorialBareMetalSW/digilentTutorialBareMetalSW.srcs/constrs_1/imports/user/Nexys-A7-100T-Master.xdc":74]

The tutorial is a great tutorial and does reference errors that may occur in some steps, however there is no reference to this error and what to do.

I guess I have to modify some clock settings. Any help would be appreciated.

Kind regards,

Rochus
 

[artvvb]

Hi @Rochus

The critical error indicates that two ports have been constrained to use the same pin location, which is not allowed as it could result in problems like nets being driven by multiple sources. Timing issues that arise while the location constraint issue is present won't necessarily indicate any issues with the final design - the tool could be trying to do something weird to fix an otherwise untenable situation.

In short, you need to use any of the other buttons on the Nexys A7, because the CPU_RESETN port is the same one that is connected through the "Reset" board interface.

I've split the Nexys A7's CPU reset button out from the rest of its buttons in the Github repo, to better indicate that this button is different, so that this error will be more easily avoided with new downloads of the digilent-xdc-master ZIP.

Thanks!

Arthur

 

[Rochus]

Hi @artvvb,

thanks for your reply.

I think I understand what you are saying.

The tutorial is a generic board tutorial. There is a section in the tutorial that instructs the user to assign buttons to GPIOs, and I assigned all of them but I did think it is a bit weird that that the reset button should be assigned. 

I will make that change. 

So the file you reference in GitHub is the constraints file ? For completeness is it in this repo ? 

Thanks again,

Rochus

[artvvb]

Yes, the tutorial is generic, supporting multiple boards, and the Nexys A7's master XDC file had the reset button mixed in with the rest of its buttons. This is unlike any of the other boards the tutorial supports, which was missed when the tutorial was written.

The file that was changed was the master XDC file, found in the digilent-xdc repo. The tutorial doesn't link to directly to github, but includes a download link for a ZIP file that comes from there.

Thanks,

Arthur

[Rochus]

Thanks @artvvb

I have commented out the reset button, and made changes to the remaining buttons to use GPIO pins 0-4.

I then ran the synthesis and the implementation again but I still get timing errors. See the attachment. I guess maybe the clock setting for the tutorial is not aligned to the board too. Is this correct ?

Thanks,

Rochus