COMMUNICATION BETWEEN FPGA BOARDS using UART IP

[HAZIQ]

Hello @JColvin,

I open this new question to ask you about the communication for the fpga boards by using uart ip. Can we use the uart ip which is already given in the block design to communicate the boards ?

[JColvin]

Hi @HAZIQ,

Yes, this could be done. If you still want to be able to separately communicate with the attached host computer over serial, you'll need to create a separate UART IP. Either way (creating a separate IP or adjusting the existing IP) can be accomplished through the following:

- Open the project in whatever version of Vivado you have, and then open the Block Diagram.
- Go to the AXI Uartlite IP on the right hand side and delete the existing "usb_uart" port coming off the right hand side of the IP block.
- Double click on the AXI Uartlite IP to bring up the IP configuration wizard. In the Board tab, change the board interface dropdown from "usb uart" to "Custom" and then select OK.
- Expand the UART interface on the IP so that you see the rx and tx lines individually.
- Right click on both of them individually and select the "Make External" option. By default this will create two ports named "rx_0" and "tx_0", though you can rename them to whatever you like in the External Port Properties box in Vivado.
- Go to the Sources tab and right-click on the Constraints folder and select "Add Sources"
- Select "Add or Create Constraints" and then either add an existing Nexys A7 .xdc file (one is available Digilent's Github here: https://github.com/Digilent/digilent-xdc/blob/master/Nexys-A7-100T-Master.xdc) or you can create your own if you don't want to have a file filled with commented out lines.
- The two lines you want for TxD to be assigned to pio1 and RxD to pio2 are as follows (formatted based on lines 42 and 43 of the above linked Nexys A7 master .xdc file)

set_property -dict { PACKAGE_PIN ??? IOSTANDARD LVCMOS33 } [get_ports { tx_0 }]; #whatever IO pin you choose to send UART signals out of the Nexys A7
set_property -dict { PACKAGE_PIN ??? IOSTANDARD LVCMOS33 } [get_ports { rx_0 }]; #whatever IO pin you choose to receive UART signals into the Nexys A7

- Generate the bitstream

 

Realistically, this will probably be a far easier approach to facilitate communication between two boards than attempting to manage and fine tune a wireless software stack that was designed for a processor on a processor that is, from a certain point of view, being emulated.

Let me know if you have any questions.

Thanks,
JColvin

[HAZIQ]

Dear @JColvin,

Thank you for your reply. Really appreciated, so now I have construct the block diagram as you mentioned, but I am not really understand about the pin that I need to set, as far as my knowledge, if I want to setup the uart, I need to set the pin according to the nexys-7 tx and rx which is C4 and D4. Lets say i manage to set the pin, how can i communicate between each board ? Did i need to write some codes in the sdk ?. I really need your help on this one. Thank you so much for your help.

Best regards,

Haziq

[HAZIQ]

Another extra question. Did i need to setup the microblaze block ip for this uart communication ?

[HAZIQ]

Dear @JColvin,

Any update on my question about the pin ? I'm sorry to ask you many time.

Best Regards,

Haziq

[rjr1287]

I think the point was that you could use some other pins to allow you to have two UARTs, one to connect to the other board, as you want, and another one to connect to a computer, if that's needed. You would need to create a cable to go from the two pins on one board to the two pins on the other board (output to input), but you would need that even if you used the standard pins. I'm not familiar with the board you're using, but if C4 is the output pin and D4 is the input pin (on both boards), you would need to wire it up so that C4 on one board is connected to D4 on the other board.

Since the UART IP uses the AXI interface, it might be easiest to have a MicroBlaze processor to move the data from one address space to another, but I would bet there is a way to do it completely within the FPGA (I'm not an expert). Or, I've found simple UART VHDL code available (search the internet) that has a much simpler interface. Data movement can be done completely within the FPGA very easily.